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Fix whitespace

This commit is contained in:
mrg 2022-10-20 16:38:23 -07:00
parent 8fd08916a1
commit 9b6eb4a120
2 changed files with 1 additions and 3 deletions
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2
compiler/drc/custom_cell_properties.py
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@ -233,7 +233,7 @@ class cell_properties():
self._row_cap_2port = bitcell(["wl0", "wl1", "gnd"], self._row_cap_2port = bitcell(["wl0", "wl1", "gnd"],
["INPUT", "INPUT", "POWER", "GROUND"]) ["INPUT", "INPUT", "POWER", "GROUND"])
self._internal = cell([],[]) self._internal = cell([],[])
@property @property

2
compiler/modules/internal_base.py
View File

@ -12,5 +12,3 @@ class internal_base(design):
def __init__(self, name, cell_name=None, prop=None): def __init__(self, name, cell_name=None, prop=None):
design.__init__(self, name, cell_name, prop) design.__init__(self, name, cell_name, prop)