mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed formatting on all files
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@ -25,14 +25,9 @@ class sram_1bank(design, verilog, lef):
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Procedures specific to a one bank SRAM.
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"""
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def __init__(self, name, sram_config):
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print("sram_1bank debug: init")
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design.__init__(self, name)
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print("sram_1bank debug: design init")
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lef.__init__(self, ["m1", "m2", "m3", "m4"])
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print("sram_1bank debug: lef init")
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verilog.__init__(self)
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print("sram_1bank debug: verilog init")
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self.sram_config = sram_config
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sram_config.set_local_config(self)
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