From 9a36cce7ae7ed712691fbee28bbf1bd44e9ebb49 Mon Sep 17 00:00:00 2001
From: Gary Mejia <gmejiama@ucsc.edu>
Date: Wed, 14 Jun 2023 12:28:36 -0700
Subject: [PATCH] Fixed formatting on all files

---
 compiler/base/rom_verilog.py   | 6 +++---
 compiler/modules/sram_1bank.py | 5 -----
 compiler/rom.py                | 2 +-
 3 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/compiler/base/rom_verilog.py b/compiler/base/rom_verilog.py
index 421ceb69..f914b539 100644
--- a/compiler/base/rom_verilog.py
+++ b/compiler/base/rom_verilog.py
@@ -23,7 +23,7 @@ class rom_verilog:
 
         self.vf.write("// OpenROM ROM model\n")
 
-        #basic info 
+        #basic info
         self.vf.write("// Words: {0}\n".format(self.num_words))
         self.vf.write("// Word size: {0}\n".format(self.word_size))
         self.vf.write("// Word per Row: {0}\n".format(self.words_per_row))
@@ -40,7 +40,7 @@ class rom_verilog:
             self.gnd_name = spice["ground"]
         except KeyError:
             self.gnd_name = "gnd"
-        
+
         #add multiple banks later
         self.vf.write("module {0}(\n".format(self.name))
         self.vf.write("`ifdef USE_POWER_PINS\n")
@@ -88,7 +88,7 @@ class rom_verilog:
         else:
             raise ValueError(f"Data type: {self.data_type} is not supported!")
         self.vf.write(f"  end\n\n")
-            
+
         for port in self.all_ports:
             self.register_inputs(port)
 
diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py
index 2302a162..4be9762a 100644
--- a/compiler/modules/sram_1bank.py
+++ b/compiler/modules/sram_1bank.py
@@ -25,14 +25,9 @@ class sram_1bank(design, verilog, lef):
     Procedures specific to a one bank SRAM.
     """
     def __init__(self, name, sram_config):
-        print("sram_1bank debug: init")
         design.__init__(self, name)
-        print("sram_1bank debug: design init")
         lef.__init__(self, ["m1", "m2", "m3", "m4"])
-        print("sram_1bank debug: lef init")
         verilog.__init__(self)
-        print("sram_1bank debug: verilog init")
-
         self.sram_config = sram_config
         sram_config.set_local_config(self)
 
diff --git a/compiler/rom.py b/compiler/rom.py
index 37954457..b997f088 100644
--- a/compiler/rom.py
+++ b/compiler/rom.py
@@ -48,7 +48,7 @@ class rom():
         import openram.modules.rom_bank as rom
 
         self.r = rom(name, rom_config)
-        
+
         self.r.create_netlist()
         if not OPTS.netlist_only:
             self.r.create_layout()