diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 8be98666..faf8d64a 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -382,9 +382,8 @@ class bank(design.design): self.bitcell_array = factory.create(module_type="replica_bitcell_array", cols=self.num_cols + self.num_spare_cols, rows=self.num_rows, - left_rbl=1, - right_rbl=1 if len(self.all_ports)>1 else 0, - bitcell_ports=self.all_ports) + rbl=[1, 1 if len(self.all_ports)>1 else 0]) + self.add_mod(self.bitcell_array) if(self.num_banks > 1): diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index 728f170f..6035fae5 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -16,13 +16,11 @@ class global_bitcell_array(bitcell_base_array): Creates a global bitcell array with a number of local arrays of a sizes given by a tuple in the list. """ - def __init__(self, sizes, name=""): - # Each bank will have the same number of rows - self.rows = sizes[0][0] - for (r, c) in sizes: - debug.check(r[0] == self.rows, "Cannot have non-uniform number of rows in global array.") + def __init__(self, rows, cols, ports, add_replica, name=""): # The total of all columns will be the number of columns - self.cols = sum(x[1] for x in sizes) + self.cols = sum(cols) + self.local_cols = cols + self.rows = rows self.sizes = sizes super().__init__(rows=self.rows, cols=self.cols, name=name) @@ -49,9 +47,15 @@ class global_bitcell_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ self.local_mods = [] - for (row, col) in self.sizes: - la = factory.create(module_type="local_bitcell_array", rows=row, cols=col) - self.add_mod(la) + for i, col in enumerate(self.local_cols): + if i==self.add_replica[0]: + la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, left_rbl=i, add_replica=True) + elif len(self.add_replica)==2 and i==self.add_replica[2]: + la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, left_rbl=i, add_replica=True) + else: + la = factory.create(module_type="local_bitcell_array", rows=row, cols=col, add_replica=False) + + self.add_mod(la) self.local_mods.append(la) def create_instances(self): diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index cf5fbdee..6b96dde6 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -18,15 +18,16 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): This can either be a single aray on its own if there is no hierarchical WL or it can be combined into a larger array with hierarchical WL. """ - def __init__(self, rows, cols, ports, left_rbl=0, right_rbl=0, add_replica=True, name=""): + def __init__(self, rows, cols, rbl, add_rbl=None, name=""): super().__init__(name, rows, cols, 0) debug.info(2, "create local array of size {} rows x {} cols words".format(rows, - cols + left_rbl + right_rbl)) + cols + sum(rbl))) self.rows = rows self.cols = cols - self.add_replica=add_replica - self.all_ports = ports + self.rbl = rbl + if add_rbl == None: + self.add_rbl = rbl self.create_netlist() if not OPTS.netlist_only: @@ -62,10 +63,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): self.bitcell_array = factory.create(module_type="replica_bitcell_array", cols=self.cols, rows=self.rows, - left_rbl=1, - right_rbl=1 if len(self.all_ports)>1 else 0, - bitcell_ports=self.all_ports, - add_replica=self.add_replica) + rbl=self.rbl) self.add_mod(self.bitcell_array) self.wl_array = factory.create(module_type="wordline_buffer_array", diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 1abd5553..dd5b83f4 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -21,34 +21,32 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): Requires a regular bitcell array, replica bitcell, and dummy bitcell (Bl/BR disconnected). """ - def __init__(self, rows, cols, left_rbl, right_rbl, bitcell_ports, name, add_replica=True): + def __init__(self, rows, cols, rbl, name, add_rbl=None): super().__init__(name, rows, cols, column_offset=0) debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) self.add_comment("rows: {0} cols: {1}".format(rows, cols)) self.column_size = cols self.row_size = rows - self.left_rbl = left_rbl - self.right_rbl = right_rbl - self.bitcell_ports = bitcell_ports - # If set to false, we increase the height for the replica wordline row, but don't - # actually add the column to this array. This is so the height matches other - # banks that have the replica columns. - # Number of replica columns to actually add - if add_replica: - self.add_left_rbl = self.left_rbl - self.add_right_rbl = self.right_rbl + # This is how many RBLs are in all the arrays + self.left_rbl = rbl[0] + self.right_rbl = rbl[1] + # This is how many RBLs are added to THIS array + if add_rbl == None: + self.add_left_rbl = rbl[0] + self.add_right_rbl = rbl[1] else: - self.add_left_rbl = 0 - self.add_right_rbl = 0 + self.add_left_rbl = add_rbl[0] + self.add_right_rbl = add_rbl[1] + for a, b in zip(add_rbl, rbl): + debug.check(a <= b, + "Invalid number of RBLs for port configuration.") - debug.check(left_rbl + right_rbl <= len(self.all_ports), + debug.check(sum(rbl) <= len(self.all_ports), "Invalid number of RBLs for port configuration.") - debug.check(left_rbl + right_rbl <= len(self.bitcell_ports), - "Bitcell ports must match total RBLs.") # Two dummy rows plus replica even if we don't add the column - self.extra_rows = 2 + self.left_rbl + self.right_rbl + self.extra_rows = 2 + sum(rbl) # Two dummy cols plus replica if we add the column self.extra_cols = 2 + self.add_left_rbl + self.add_right_rbl @@ -198,7 +196,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))] right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))] # Keep track of the left pins that are the RBL - self.replica_bl_names[port]=left_names[self.bitcell_ports[port]] + self.replica_bl_names[port]=left_names[self.all_ports[port]] # Interleave the left and right lists bitline_names = [x for t in zip(left_names, right_names) for x in t] self.replica_bitline_names[port] = bitline_names diff --git a/compiler/tests/05_local_bitcell_array_test.py b/compiler/tests/05_local_bitcell_array_test.py index 664d9ef8..9200f5bf 100755 --- a/compiler/tests/05_local_bitcell_array_test.py +++ b/compiler/tests/05_local_bitcell_array_test.py @@ -23,11 +23,11 @@ class local_bitcell_array_test(openram_test): globals.init_openram(config_file) debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica") - a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, ports=[0], add_replica=False) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[0, 0]) self.local_check(a) debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column") - a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0]) + a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0]) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py index bfb35cd7..ca10b9cb 100755 --- a/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_1rw_1r_test.py @@ -28,19 +28,15 @@ class replica_bitcell_array_1rw_1r_test(openram_test): a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, - left_rbl=1, - right_rbl=1, - bitcell_ports=[0, 1], - add_replica=False) + rbl=[1, 1], + add_rbl=[0, 0]) self.local_check(a) debug.info(2, "Testing 4x4 array for cell_1rw_1r") a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, - left_rbl=1, - right_rbl=1, - bitcell_ports=[0, 1]) + rbl=[1, 1]) self.local_check(a) @@ -50,9 +46,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test): a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, - left_rbl=2, - right_rbl=0, - bitcell_ports=[0, 1]) + rbl=[2, 0]) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py index d229b99c..22b3a926 100755 --- a/compiler/tests/14_replica_bitcell_array_test.py +++ b/compiler/tests/14_replica_bitcell_array_test.py @@ -25,7 +25,7 @@ class replica_bitcell_array_test(openram_test): factory.reset() debug.info(2, "Testing 4x4 array for bitcell") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0]) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_column_1rw_1r_test.py b/compiler/tests/14_replica_column_1rw_1r_test.py index 3c1a0e1e..335666d7 100755 --- a/compiler/tests/14_replica_column_1rw_1r_test.py +++ b/compiler/tests/14_replica_column_1rw_1r_test.py @@ -25,15 +25,15 @@ class replica_column_test(openram_test): globals.setup_bitcell() debug.info(2, "Testing replica column for 6t_cell") - a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1) + a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1) self.local_check(a) debug.info(2, "Testing replica column for 6t_cell") - a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=1, replica_bit=6) + a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6) self.local_check(a) debug.info(2, "Testing replica column for 6t_cell") - a = factory.create(module_type="replica_column", rows=4, left_rbl=2, right_rbl=0, replica_bit=2) + a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py index 57c92e84..eb1e96f7 100755 --- a/compiler/tests/14_replica_column_test.py +++ b/compiler/tests/14_replica_column_test.py @@ -20,15 +20,15 @@ class replica_column_test(openram_test): globals.init_openram(config_file) debug.info(2, "Testing replica column for 6t_cell") - a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1) + a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1) self.local_check(a) debug.info(2, "Testing replica column for 6t_cell") - a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=1, replica_bit=6) + a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6) self.local_check(a) debug.info(2, "Testing replica column for 6t_cell") - a = factory.create(module_type="replica_column", rows=4, left_rbl=2, right_rbl=0, replica_bit=2) + a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py index 6a87f408..8376241c 100755 --- a/compiler/tests/14_replica_pbitcell_array_test.py +++ b/compiler/tests/14_replica_pbitcell_array_test.py @@ -27,7 +27,7 @@ class replica_pbitcell_array_test(openram_test): OPTS.num_w_ports = 0 debug.info(2, "Testing 4x4 array for pbitcell") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0,1]) + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], add_rbl=[1, 1]) self.local_check(a) OPTS.bitcell = "pbitcell" @@ -39,7 +39,7 @@ class replica_pbitcell_array_test(openram_test): factory.reset() debug.info(2, "Testing 4x4 array for pbitcell") - a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0]) + a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0], add_rbl=[1, 0]) self.local_check(a) globals.end_openram()