diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py
index 77a6932c..ae0668ae 100755
--- a/compiler/tests/04_pnand2_test.py
+++ b/compiler/tests/04_pnand2_test.py
@@ -25,10 +25,10 @@ class pnand2_test(openram_test):
         tx = factory.create(module_type="pnand2", size=1)
         self.local_check(tx)
 
-        debug.info(2, "Checking 2-input nand gate")
-        tx = factory.create(module_type="pnand2", size=1, add_wells=False)
-        # Only DRC because well contacts will fail LVS
-        self.local_drc_check(tx)
+        # debug.info(2, "Checking 2-input nand gate")
+        # tx = factory.create(module_type="pnand2", size=1, add_wells=False)
+        # # Only DRC because well contacts will fail LVS
+        # self.local_drc_check(tx)
         
         globals.end_openram()
         
diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py
index 82bf1846..c03e32d6 100755
--- a/compiler/tests/04_pnand3_test.py
+++ b/compiler/tests/04_pnand3_test.py
@@ -25,10 +25,10 @@ class pnand3_test(openram_test):
         tx = factory.create(module_type="pnand3", size=1)
         self.local_check(tx)
 
-        debug.info(2, "Checking 3-input nand gate")
-        tx = factory.create(module_type="pnand3", size=1, add_wells=False)
-        # Only DRC because well contacts will fail LVS
-        self.local_drc_check(tx)
+        # debug.info(2, "Checking 3-input nand gate")
+        # tx = factory.create(module_type="pnand3", size=1, add_wells=False)
+        # # Only DRC because well contacts will fail LVS
+        # self.local_drc_check(tx)
 
         globals.end_openram()