luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 11:08:01 +02:00
Code Issues Packages Projects Releases Wiki Activity

Add preferred direction to via1, routed between supply lines in wmask AND array, and only uses m3 for channel route with a write mask.

Browse Source
This commit is contained in:
jsowash
2019-08-21 14:02:57 -07:00
parent 4f01eeb3c1
commit 980760b724
2 changed files with 35 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/write_mask_and_array.py
+7 -1
View File
@@ -123,6 +123,7 @@ class write_mask_and_array(design.design):
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=en_pin.center())
# Route en pin between AND gates
if i < self.num_wmasks-1:
self.add_layout_pin(text="en",
layer="metal3",
@@ -137,10 +138,15 @@ class write_mask_and_array(design.design):
width=wmask_out_pin.width(),
height=wmask_out_pin.height())
self.add_power_pin("gnd", vector((supply_pin.lx() - 0.75 *drc('minwidth_metal1'))+i*self.wmask_en_len,
self.add_power_pin("gnd", vector((supply_pin.lx() - 0.75*drc('minwidth_metal1'))+i*self.wmask_en_len,
0))
self.add_power_pin("vdd", vector((supply_pin.lx() - 0.75*drc('minwidth_metal1'))+i*self.wmask_en_len,
self.height))
if i < self.num_wmasks-1:
for n in ["gnd","vdd"]:
pin = self.and2_insts[i].get_pin(n)
next_pin = self.and2_insts[i+1].get_pin(n)
self.add_path("metal1",[pin.center(),next_pin.center()])
def en_width(self, pin):