From 9717794400abca290a035040cfd972eb25187757 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 8 Dec 2020 11:59:14 -0800 Subject: [PATCH] Remove extra debug statement --- compiler/tests/05_bitcell_array_1rw_1r_test.py | 4 ++-- compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py | 1 + compiler/verify/magic.py | 1 - 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/tests/05_bitcell_array_1rw_1r_test.py b/compiler/tests/05_bitcell_array_1rw_1r_test.py index 32207ab5..a0d05574 100755 --- a/compiler/tests/05_bitcell_array_1rw_1r_test.py +++ b/compiler/tests/05_bitcell_array_1rw_1r_test.py @@ -27,8 +27,8 @@ class bitcell_array_1rw_1r_test(openram_test): OPTS.num_w_ports = 0 globals.setup_bitcell() - debug.info(2, "Testing 4x4 array for cell_1rw_1r") - a = factory.create(module_type="bitcell_array", cols=4, rows=4) + debug.info(2, "Testing 2x2 array for cell_2port") + a = factory.create(module_type="bitcell_array", cols=2, rows=2) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index bac2fd5f..b8d90ad0 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -23,6 +23,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config + OPTS.route_supplies = False OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 8080a87d..8cc0cf92 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -153,7 +153,6 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa from tech import blackbox_cells except ImportError: blackbox_cells = [] - import pdb; pdb.set_trace() for cell_name in blackbox_cells: mag_file = OPTS.openram_tech + "maglef_lib/" + cell_name + ".mag" debug.check(os.path.isfile(mag_file), "Could not find blackbox cell {}".format(mag_file))