From 969cca28e4d94a4baec6cdc9522d1842a2f21aab Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 6 Sep 2019 07:16:50 -0700 Subject: [PATCH] Enable sensing during writes. Need to add dedicated test. --- compiler/characterizer/functional.py | 6 +++--- compiler/modules/control_logic.py | 14 +++----------- 2 files changed, 6 insertions(+), 14 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 49907b4b..a9489b23 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -70,7 +70,7 @@ class functional(simulation): if feasible_period: #period defaults to tech.py feasible period otherwise. self.period = feasible_period # Generate a random sequence of reads and writes - self.write_random_memory_sequence() + self.create_random_memory_sequence() # Run SPICE simulation self.write_functional_stimulus() @@ -84,7 +84,7 @@ class functional(simulation): # Check read values with written values. If the values do not match, return an error. return self.check_stim_results() - def write_random_memory_sequence(self): + def create_random_memory_sequence(self): if self.write_size: rw_ops = ["noop", "write", "partial_write", "read"] w_ops = ["noop", "write", "partial_write"] @@ -187,7 +187,7 @@ class functional(simulation): self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks) def read_stim_results(self): - # Extrat dout values from spice timing.lis + # Extract dout values from spice timing.lis for (word, dout_port, eo_period, check) in self.write_check: sp_read_value = "" for bit in range(self.word_size): diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 06883125..20f4997f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -639,14 +639,11 @@ class control_logic(design.design): def create_sen_row(self): """ Create the sense enable buffer. """ - if self.port_type=="rw": - input_name = "we_bar" - else: - input_name = "cs_bar" # GATE FOR S_EN + # Uses cs_bar (not we_bar) for feed-thru reads self.s_en_gate_inst = self.add_inst(name="buf_s_en_and", mod=self.sen_and3) - self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"]) + self.connect_inst(["rbl_bl_delay", "gated_clk_bar", "cs_bar", "s_en", "vdd", "gnd"]) def place_sen_row(self,row): @@ -659,12 +656,7 @@ class control_logic(design.design): def route_sen(self): - if self.port_type=="rw": - input_name = "we_bar" - else: - input_name = "cs_bar" - - sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", input_name]) + sen_map = zip(["A", "B", "C"], ["rbl_bl_delay", "gated_clk_bar", "cs_bar"]) self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets) self.connect_output(self.s_en_gate_inst, "Z", "s_en")