Add extra dnwell spacing for single port

2021-06-23 11:14:58 -07:00 · 2021-06-23 11:14:58 -07:00 · 958f5e45bb
parent ef733bb7aa
commit 958f5e45bb
1 changed files with 2 additions and 2 deletions
--- a/compiler/sram/sram_1bank.py
+++ b/compiler/sram/sram_1bank.py
@ -334,7 +334,7 @@ class sram_1bank(sram_base):
        self.add_layout_pins()

        # Some technologies have an isolation
-        self.add_dnwell(inflate=2)
+        self.add_dnwell(inflate=2.5)

        # We need the initial bbox for the supply rings later
        # because the perimeter pins will change the bbox