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Add extra dnwell spacing for single port

This commit is contained in:
mrg 2021-06-23 11:14:58 -07:00
parent ef733bb7aa
commit 958f5e45bb
1 changed files with 2 additions and 2 deletions
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4
compiler/sram/sram_1bank.py
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@ -334,7 +334,7 @@ class sram_1bank(sram_base):
self.add_layout_pins() self.add_layout_pins()
# Some technologies have an isolation # Some technologies have an isolation
self.add_dnwell(inflate=2) self.add_dnwell(inflate=2.5)
# We need the initial bbox for the supply rings later # We need the initial bbox for the supply rings later
# because the perimeter pins will change the bbox # because the perimeter pins will change the bbox
@ -642,7 +642,7 @@ class sram_1bank(sram_base):
# Insts located in control logic, exclusion function called here # Insts located in control logic, exclusion function called here
for inst in self.control_logic_insts: for inst in self.control_logic_insts:
inst.mod.graph_exclude_dffs() inst.mod.graph_exclude_dffs()
def get_cell_name(self, inst_name, row, col): def get_cell_name(self, inst_name, row, col):
""" """
Gets the spice name of the target bitcell. Gets the spice name of the target bitcell.