Consolidate metal pitch rules to new design class

compiler/modules/bank.py

@@ -161,10 +161,6 @@ class bank(design.design):
         else:
             self.num_col_addr_lines = 0            
 
-        # M1/M2 routing pitch is based on contacted pitch
-        self.m1_pitch = contact.m1m2.height + max(self.m1_space,self.m2_space)
-        self.m2_pitch = contact.m2m3.height + max(self.m2_space,self.m3_space)
-
         # The width of this bus is needed to place other modules (e.g. decoder)
         # A width on each side too
         self.central_bus_width = self.m2_pitch * self.num_control_lines + 2*self.m2_width

compiler/modules/bank_select.py

@@ -56,10 +56,6 @@ class bank_select(design.design):
 
     def calculate_module_offsets(self):
         
-        # M1/M2 routing pitch is based on contacted pitch
-        self.m1_pitch = contact.m1m2.height + max(self.m1_space,self.m2_space)
-        self.m2_pitch = contact.m2m3.height + max(self.m2_space,self.m3_space)
-
         self.xoffset_nand =  self.inv4x.width + 2*self.m2_pitch + drc["pwell_to_nwell"]
         self.xoffset_nor =  self.inv4x.width + 2*self.m2_pitch + drc["pwell_to_nwell"]
         self.xoffset_inv = max(self.xoffset_nand + self.nand2.width, self.xoffset_nor + self.nor2.width) 

compiler/modules/control_logic.py

@@ -86,10 +86,6 @@ class control_logic(design.design):
         # These aren't for instantiating, but we use them to get the dimensions
         #self.poly_contact_offset = vector(0.5*contact.poly.width,0.5*contact.poly.height)
 
-        # M1/M2 routing pitch is based on contacted pitch
-        self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(drc["metal1_to_metal1"],drc["metal2_to_metal2"])
-        self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(drc["metal2_to_metal2"],drc["metal3_to_metal3"])
-
         # Have the cell gap leave enough room to route an M2 wire.
         # Some cells may have pwell/nwell spacing problems too when the wells are different heights.
         #self.cell_gap = max(self.m2_pitch,drc["pwell_to_nwell"])

compiler/modules/hierarchical_decoder.py

@@ -90,9 +90,6 @@ class hierarchical_decoder(design.design):
             debug.error("Invalid number of inputs for hierarchical decoder",-1)
 
     def setup_layout_constants(self):
-        self.m1_pitch = contact.m1m2.height + max(self.m1_space,self.m2_space)
-        self.m2_pitch = contact.m2m3.height + max(self.m2_space,self.m3_space)
-
         self.predec_groups = []  # This array is a 2D array.
 
         # Distributing vertical rails to different groups. One group belongs to one pre-decoder.

compiler/modules/hierarchical_predecode.py

@@ -50,10 +50,6 @@ class hierarchical_predecode(design.design):
             debug.error("Invalid number of predecode inputs.",-1)
             
     def setup_constraints(self):
-        # use a conservative douple spacing just to get rid of annoying via DRCs
-        self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space)
-        self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space,self.m3_space)
-        
         # The rail offsets are indexed by the label
         self.rails = {}
 

compiler/modules/replica_bitline.py

@@ -53,11 +53,6 @@ class replica_bitline(design.design):
         # These aren't for instantiating, but we use them to get the dimensions
         self.poly_contact_offset = vector(0.5*contact.poly.width,0.5*contact.poly.height)
 
-        # M1/M2 routing pitch is based on contacted pitch
-        self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space,self.m2_space)
-        self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space,self.m3_space)
-
-        
         # Quadrant 1: Replica bitline and such are not rotated, but they must be placed far enough
         # away from the delay chain/inverter with space for three M2 tracks
         self.bitcell_offset = vector(0,self.replica_bitcell.height)

compiler/modules/single_level_column_mux_array.py

@@ -57,7 +57,6 @@ class single_level_column_mux_array(design.design):
     def setup_layout_constants(self):
         self.column_addr_size = num_of_inputs = int(self.words_per_row / 2)
         self.width = self.columns * self.mux.width
-        self.m1_pitch = contact.m1m2.width + max(drc["metal1_to_metal1"],drc["metal2_to_metal2"])
         # one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
         # one extra route pitch is to space from the sense amp
         self.route_height = (self.words_per_row + 3)*self.m1_pitch