mirror of https://github.com/VLSIDA/OpenRAM.git
Fix power pin layer problems in delay line
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@ -178,10 +178,14 @@ class delay_chain(design.design):
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load_list = self.load_inst_map[inst]
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for pin_name in ["vdd", "gnd"]:
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pin = load_list[0].get_pin(pin_name)
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self.add_power_pin(pin_name, pin.rc() - vector(self.m1_pitch, 0))
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self.add_power_pin(pin_name,
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pin.rc() - vector(self.m1_pitch, 0),
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start_layer=pin.layer)
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pin = load_list[-1].get_pin(pin_name)
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self.add_power_pin(pin_name, pin.rc() - vector(0.5 * self.m1_pitch, 0))
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pin = load_list[-2].get_pin(pin_name)
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self.add_power_pin(pin_name,
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pin.rc() - vector(self.m1_pitch, 0),
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start_layer=pin.layer)
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def add_layout_pins(self):
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