luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

allow spare col number override

This commit is contained in:
Jesse Cirimelli-Low 2021-05-03 21:59:05 -07:00
parent a7d0a1ef3a
commit 93b264bc4c
1 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
compiler/modules/port_data.py
View File

@ -22,7 +22,6 @@ class port_data(design.design):
""" """
def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False): def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False):
sram_config.set_local_config(self) sram_config.set_local_config(self)
if dimension_override: if dimension_override:
self.num_rows = rows self.num_rows = rows
@ -35,10 +34,9 @@ class port_data(design.design):
else: else:
self.num_wmasks = 0 self.num_wmasks = 0
if num_spare_cols is not None:
self.num_spare_cols = num_spare_cols + self.num_spare_cols if self.num_spare_cols is None or self.num_spare_cols is 0:
if self.num_spare_cols is None: self.num_spare_cols = num_spare_cols
self.num_spare_cols = 0
if not bit_offsets: if not bit_offsets:
bitcell = factory.create(module_type=OPTS.bitcell) bitcell = factory.create(module_type=OPTS.bitcell)
if(cell_properties.use_strap == True and OPTS.num_ports == 1): if(cell_properties.use_strap == True and OPTS.num_ports == 1):