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Merge remote-tracking branch 'origin/dev' into supply_routing

This commit is contained in:
Matt Guthaus 2018-09-05 11:05:41 -07:00
parent 2a27fbc98e ba651d53ae
commit 93b24d8c85
2 changed files with 30 additions and 30 deletions
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60
compiler/tests/04_pbitcell_test.py
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@ -20,72 +20,72 @@ class pbitcell_test(openram_test):
globals.init_openram("config_20_{0}".format(OPTS.tech_name)) globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from pbitcell import pbitcell from pbitcell import pbitcell
import tech import tech
OPTS.sram_config.num_rw_ports=1 OPTS.num_rw_ports=1
OPTS.sram_config.num_w_ports=1 OPTS.num_w_ports=1
OPTS.sram_config.num_r_ports=1 OPTS.num_r_ports=1
debug.info(2, "Bitcell with 1 of each port: read/write, write, and read") debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=0 OPTS.num_rw_ports=0
OPTS.sram_config.num_w_ports=1 OPTS.num_w_ports=1
OPTS.sram_config.num_r_ports=1 OPTS.num_r_ports=1
debug.info(2, "Bitcell with 0 read/write ports") debug.info(2, "Bitcell with 0 read/write ports")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=1 OPTS.num_rw_ports=1
OPTS.sram_config.num_w_ports=0 OPTS.num_w_ports=0
OPTS.sram_config.num_r_ports=1 OPTS.num_r_ports=1
debug.info(2, "Bitcell with 0 write ports") debug.info(2, "Bitcell with 0 write ports")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=1 OPTS.num_rw_ports=1
OPTS.sram_config.num_w_ports=1 OPTS.num_w_ports=1
OPTS.sram_config.num_r_ports=0 OPTS.num_r_ports=0
debug.info(2, "Bitcell with 0 read ports") debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=1 OPTS.num_rw_ports=1
OPTS.sram_config.num_w_ports=0 OPTS.num_w_ports=0
OPTS.sram_config.num_r_ports=0 OPTS.num_r_ports=0
debug.info(2, "Bitcell with 0 read ports and 0 write ports") debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=2 OPTS.num_rw_ports=2
OPTS.sram_config.num_w_ports=2 OPTS.num_w_ports=2
OPTS.sram_config.num_r_ports=2 OPTS.num_r_ports=2
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read") debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=0 OPTS.num_rw_ports=0
OPTS.sram_config.num_w_ports=2 OPTS.num_w_ports=2
OPTS.sram_config.num_r_ports=2 OPTS.num_r_ports=2
debug.info(2, "Bitcell with 0 read/write ports") debug.info(2, "Bitcell with 0 read/write ports")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=2 OPTS.num_rw_ports=2
OPTS.sram_config.num_w_ports=0 OPTS.num_w_ports=0
OPTS.sram_config.num_r_ports=2 OPTS.num_r_ports=2
debug.info(2, "Bitcell with 0 write ports") debug.info(2, "Bitcell with 0 write ports")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=2 OPTS.num_rw_ports=2
OPTS.sram_config.num_w_ports=2 OPTS.num_w_ports=2
OPTS.sram_config.num_r_ports=0 OPTS.num_r_ports=0
debug.info(2, "Bitcell with 0 read ports") debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)
OPTS.sram_config.num_rw_ports=2 OPTS.num_rw_ports=2
OPTS.sram_config.num_w_ports=0 OPTS.num_w_ports=0
OPTS.sram_config.num_r_ports=0 OPTS.num_r_ports=0
debug.info(2, "Bitcell with 0 read ports and 0 write ports") debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = pbitcell() tx = pbitcell()
self.local_check(tx) self.local_check(tx)

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technology/freepdk45/gds_lib/replica_cell_6t.gds
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