From d721fae5b0014de292080610180f2aa17872565e Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 4 Sep 2018 14:33:14 -0700 Subject: [PATCH 1/2] Change labels in replica cell for freepdk45 too --- .../freepdk45/gds_lib/replica_cell_6t.gds | Bin 20480 -> 20480 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/freepdk45/gds_lib/replica_cell_6t.gds b/technology/freepdk45/gds_lib/replica_cell_6t.gds index 9b301c08ae8f2b857d6cbdef1795cc73b82ea61a..2881a883709d5f4b04a8632ed039b1c2e7e61b9c 100644 GIT binary patch delta 961 zcmYLGPiPZa9G*9wPA6&Fnl@>gKWemC-6en8Ce|iRXWmT5aio)O+3kWXi(pX?Qe=^p zJrwE?N*WJJ>nDilK`7qDgQH#w5<;0q@F3!0PagCt9;A3FEc@FY*2Bm9e((2v-}}Ay z+(*oP#Ma}d1A-*<3TYuLghct`rOOwtFa0S9k&aF^z5U?vr(eF6j{Y8dTYd6YNOg*& z>=tApC`5&EpD@AS1h8@VIU}uVNaUF zYiSyFX$EH{QcEV@kj@eFn|pl>%YC!IVOsb$5gCNnx37%!sw_oc)>ZY^I33iK;$Z# znt__eVQA_dqAgX0s~Rv=4w2BBrq;BJR>eiFLcC(Y)GJ<7cNtvWggL`K>C8V2Elc(I z=^EQ?=?tPtvYA(2OQ-Q%o$?5h{v%#GS)7`S!LR;-r&SYI2qT1#&L~!#dE^KmX6JF6 VkaG^;x7p(UIyjs1=H{NUe*s1~O0@t0 delta 949 zcmYjNU1%It7@a#iJDuHRH`#QPY&MCpR*Tte_h;Oul%_D6t zu4`#+L^HLdHmTX#1eO14_cmXKsh`22=%6oJxFDK)(Z_o`HdbO1Pj%kvxA8D$qaAaR zj4M1aByJmZct#5eqk&;;^`G*?afut_9eCtuY!`2hZNVH(i(GOWQNlqlq2MLxXVK5vhGj86CebIXW4rjw+(tkC zJ60w*YGwmJW*X>a=%4uzPkDDZ(Loe{1vl~%EBV(jny(|8p?=1NKU0UrILi6>Bv*r% zqbK8s(>3&`CA?`LS;o;6>!*BNnX18>YGG&cCag)$on?LY2+?uA6W($5DP-_dsf@#X z3cZqp;anP*OE!!W|FL)#wbRS`n?9Zt+qhP^f_~9~S?nTO;#Zfrszq*esfnn-HiafU za)N9X1IpQMk!xB|VKo1dK=0H5)+x^Mk_^4)ga|L3yeVLvbi(0_F@c>E9P>o5AI%Fy z3mkFb|Jr%ZGfzVznq%`h=46u`&9Zow#k1Tad6+N3E*J4=Wfp&yQeoF-b7?E+HMu`H ztD}3?IauzB{jM!As7c-*{a56|u$#DFZK7LsAgdHrTex3gUSVEgUMbSOfX&k;9+$_T zb^4;5)YWAa%XMA(_^s5&xAHu$%U9t_2ZLq+Md(e5fg{l+6rno~jv5Nx2A#=zgYR_* zL0v)BoxAlj`0nC4Y+ZZ1)oxs;*<8C{%7}v_23R zc8XZu$l>;Y;GqdKO!L Date: Wed, 5 Sep 2018 10:59:41 -0700 Subject: [PATCH 2/2] Change options in pbitcell test to be global again. --- compiler/tests/04_pbitcell_test.py | 60 +++++++++++++++--------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 70f51a99..0b6bd8f5 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -20,72 +20,72 @@ class pbitcell_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) from pbitcell import pbitcell import tech - OPTS.sram_config.num_rw_ports=1 - OPTS.sram_config.num_w_ports=1 - OPTS.sram_config.num_r_ports=1 + OPTS.num_rw_ports=1 + OPTS.num_w_ports=1 + OPTS.num_r_ports=1 debug.info(2, "Bitcell with 1 of each port: read/write, write, and read") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=0 - OPTS.sram_config.num_w_ports=1 - OPTS.sram_config.num_r_ports=1 + OPTS.num_rw_ports=0 + OPTS.num_w_ports=1 + OPTS.num_r_ports=1 debug.info(2, "Bitcell with 0 read/write ports") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=1 - OPTS.sram_config.num_w_ports=0 - OPTS.sram_config.num_r_ports=1 + OPTS.num_rw_ports=1 + OPTS.num_w_ports=0 + OPTS.num_r_ports=1 debug.info(2, "Bitcell with 0 write ports") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=1 - OPTS.sram_config.num_w_ports=1 - OPTS.sram_config.num_r_ports=0 + OPTS.num_rw_ports=1 + OPTS.num_w_ports=1 + OPTS.num_r_ports=0 debug.info(2, "Bitcell with 0 read ports") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=1 - OPTS.sram_config.num_w_ports=0 - OPTS.sram_config.num_r_ports=0 + OPTS.num_rw_ports=1 + OPTS.num_w_ports=0 + OPTS.num_r_ports=0 debug.info(2, "Bitcell with 0 read ports and 0 write ports") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=2 - OPTS.sram_config.num_w_ports=2 - OPTS.sram_config.num_r_ports=2 + OPTS.num_rw_ports=2 + OPTS.num_w_ports=2 + OPTS.num_r_ports=2 debug.info(2, "Bitcell with 2 of each port: read/write, write, and read") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=0 - OPTS.sram_config.num_w_ports=2 - OPTS.sram_config.num_r_ports=2 + OPTS.num_rw_ports=0 + OPTS.num_w_ports=2 + OPTS.num_r_ports=2 debug.info(2, "Bitcell with 0 read/write ports") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=2 - OPTS.sram_config.num_w_ports=0 - OPTS.sram_config.num_r_ports=2 + OPTS.num_rw_ports=2 + OPTS.num_w_ports=0 + OPTS.num_r_ports=2 debug.info(2, "Bitcell with 0 write ports") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=2 - OPTS.sram_config.num_w_ports=2 - OPTS.sram_config.num_r_ports=0 + OPTS.num_rw_ports=2 + OPTS.num_w_ports=2 + OPTS.num_r_ports=0 debug.info(2, "Bitcell with 0 read ports") tx = pbitcell() self.local_check(tx) - OPTS.sram_config.num_rw_ports=2 - OPTS.sram_config.num_w_ports=0 - OPTS.sram_config.num_r_ports=0 + OPTS.num_rw_ports=2 + OPTS.num_w_ports=0 + OPTS.num_r_ports=0 debug.info(2, "Bitcell with 0 read ports and 0 write ports") tx = pbitcell() self.local_check(tx)