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Add vdd/gnd for all bitcells

This commit is contained in:
mrg 2021-06-29 09:37:30 -07:00
parent d2a1f6b654
commit 930cc48e16
1 changed files with 2 additions and 2 deletions
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2
compiler/modules/bitcell_base_array.py
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@ -161,9 +161,9 @@ class bitcell_base_array(design.design):
for row in range(self.row_size): for row in range(self.row_size):
for col in range(self.column_size): for col in range(self.column_size):
inst = self.cell_inst[row, col] inst = self.cell_inst[row, col]
if row == 2: #add only 1 label per col
for pin_name in ["vdd", "gnd"]: for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name) self.copy_layout_pin(inst, pin_name)
if row == 2: #add only 1 label per col
if 'VPB' in self.cell_inst[row, col].mod.pins: if 'VPB' in self.cell_inst[row, col].mod.pins:
self.add_label("gnd", inst.get_pin("vpb").layer, inst.get_pin("vpb").ll()) self.add_label("gnd", inst.get_pin("vpb").layer, inst.get_pin("vpb").ll())
if 'VNB' in self.cell_inst[row, col].mod.pins: if 'VNB' in self.cell_inst[row, col].mod.pins: