diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py
index 495d7833..1f1a8a2d 100644
--- a/compiler/modules/bitcell_base_array.py
+++ b/compiler/modules/bitcell_base_array.py
@@ -161,9 +161,9 @@ class bitcell_base_array(design.design):
         for row in range(self.row_size):
             for col in range(self.column_size):
                 inst = self.cell_inst[row, col]
+                for pin_name in ["vdd", "gnd"]:
+                    self.copy_layout_pin(inst, pin_name)
                 if row == 2: #add only 1 label per col
-                    for pin_name in ["vdd", "gnd"]:
-                        self.copy_layout_pin(inst, pin_name)
                     if 'VPB' in self.cell_inst[row, col].mod.pins:
                         self.add_label("gnd", inst.get_pin("vpb").layer, inst.get_pin("vpb").ll())
                     if 'VNB' in self.cell_inst[row, col].mod.pins: