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fix typos and standardize multiport control logic tests

This commit is contained in:
Sam Crow 2023-06-07 16:04:54 -07:00
parent afd3b782b9
commit 9256ae8c00
2 changed files with 8 additions and 7 deletions
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13
compiler/tests/16_control_logic_delay_multiport_test.py
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@ -1,10 +1,10 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
# See LICENSE for licensing information. # See LICENSE for licensing information.
# #
#Copyright (c) 2016-2021 Regents of the University of California and The Board # Copyright (c) 2016-2023 Regents of the University of California and The Board
#of Regents for the Oklahoma Agricultural and Mechanical College # of Regents for the Oklahoma Agricultural and Mechanical College
#(acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
#All rights reserved. # All rights reserved.
# #
""" """
Run a regression test on a control_logic_delay Run a regression test on a control_logic_delay
@ -12,7 +12,7 @@ Run a regression test on a control_logic_delay
import sys, os import sys, os
import unittest import unittest
from testutils import * from testutils import header,openram_test
import openram import openram
from openram import debug from openram import debug
@ -33,7 +33,7 @@ class control_logic_delay_test(openram_test):
OPTS.num_w_ports = 1 OPTS.num_w_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
debug.info(1, "Testing sample for control_logic_delay for multiport, only write control logic") debug.info(1, "Testing sample for control_logic_delay for multiport, combined read-write control logic")
a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="rw") a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a) self.local_check(a)
@ -51,6 +51,7 @@ class control_logic_delay_test(openram_test):
openram.end_openram() openram.end_openram()
# run the test from the command line # run the test from the command line
if __name__ == "__main__": if __name__ == "__main__":
(OPTS, args) = openram.parse_args() (OPTS, args) = openram.parse_args()

2
compiler/tests/16_control_logic_multiport_test.py
View File

@ -33,7 +33,7 @@ class control_logic_test(openram_test):
OPTS.num_w_ports = 1 OPTS.num_w_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only write control logic") debug.info(1, "Testing sample for control_logic for multiport, combined read-write control logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw") a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a) self.local_check(a)