diff --git a/compiler/tests/16_control_logic_delay_multiport_test.py b/compiler/tests/16_control_logic_delay_multiport_test.py
index 1cebd4b7..60bb9472 100755
--- a/compiler/tests/16_control_logic_delay_multiport_test.py
+++ b/compiler/tests/16_control_logic_delay_multiport_test.py
@@ -1,10 +1,10 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-#Copyright (c) 2016-2021 Regents of the University of California and The Board
-#of Regents for the Oklahoma Agricultural and Mechanical College
-#(acting for and on behalf of Oklahoma State University)
-#All rights reserved.
+# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
 #
 """
 Run a regression test on a control_logic_delay
@@ -12,7 +12,7 @@ Run a regression test on a control_logic_delay
 
 import sys, os
 import unittest
-from testutils import *
+from testutils import header,openram_test
 
 import openram
 from openram import debug
@@ -33,7 +33,7 @@ class control_logic_delay_test(openram_test):
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
 
-        debug.info(1, "Testing sample for control_logic_delay for multiport, only write control logic")
+        debug.info(1, "Testing sample for control_logic_delay for multiport, combined read-write control logic")
         a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
         self.local_check(a)
 
@@ -51,6 +51,7 @@ class control_logic_delay_test(openram_test):
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()
diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py
index 600740ba..daf25578 100755
--- a/compiler/tests/16_control_logic_multiport_test.py
+++ b/compiler/tests/16_control_logic_multiport_test.py
@@ -33,7 +33,7 @@ class control_logic_test(openram_test):
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
 
-        debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
+        debug.info(1, "Testing sample for control_logic for multiport, combined read-write control logic")
         a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
         self.local_check(a)