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https://github.com/VLSIDA/OpenRAM.git
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more code cleaning
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@@ -30,7 +30,6 @@ class rom_column_mux_array(design):
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self.words_per_row = int(self.columns / self.word_size)
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self.input_layer = input_layer
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self.tap_spacing = tap_spacing
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# self.sel_layer = layer_props.column_mux_array.select_layer
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self.sel_layer = sel_layer
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self.sel_pitch = getattr(self, self.sel_layer + "_pitch")
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@@ -107,12 +106,6 @@ class rom_column_mux_array(design):
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# For every column, add a pass gate
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for col_num, xoffset in enumerate(self.offsets[0:self.columns]):
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# if self.cell.mirror.y and (col_num + self.column_offset) % 2:
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# mirror = "MY"
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# xoffset = xoffset + self.mux.width
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# else:
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# mirror = ""
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offset = vector(xoffset, self.route_height)
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self.mux_inst[col_num].place(offset=offset)
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@@ -206,11 +199,6 @@ class rom_column_mux_array(design):
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offset=bl_out_offset_begin,
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directions=self.via_directions)
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def add_taps(self):
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pass
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def graph_exclude_columns(self, column_include_num):
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"""
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Excludes all columns muxes unrelated to the target bit being simulated.
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