From 9181f6a21816a6156beac34d10d7dd85e078f835 Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Mon, 3 Apr 2023 10:08:57 -0700 Subject: [PATCH] standardize 14* test structure --- .../tests/14_capped_replica_bitcell_array_dummies_1rw_test.py | 1 + .../14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py | 1 + .../tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py | 1 + .../tests/14_capped_replica_bitcell_array_norbl_1rw_test.py | 1 + .../14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py | 1 + .../tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py | 1 + compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py | 2 +- compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py | 1 + compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py | 2 +- compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py | 1 + compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py | 1 + compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py | 1 + 12 files changed, 12 insertions(+), 2 deletions(-) diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py index 6ce8a1c0..c0ff770f 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py @@ -23,6 +23,7 @@ class capped_replica_bitcell_array_dummies_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 capped replica array for 1rw cell with dummy row only") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py index 72bc698c..53b4231b 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class capped_replica_bitcell_array_leftrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py index 5d1523ae..7ed5fdf9 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py @@ -23,6 +23,7 @@ class capped_replica_bitcell_array_leftrbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 capped replica array for 1rw cell with left replica column") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py index 5eb5f98e..56080536 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py @@ -23,6 +23,7 @@ class capped_replica_bitcell_array_norbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py index 22433884..c8d322c4 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class capped_replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py index bd654d73..1386b2cc 100755 --- a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py @@ -23,6 +23,7 @@ class capped_replica_bitcell_array_rightrbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 capped replica array for 1rw cell with right replica column") a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0]) diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py index 465260b4..f5a2a3e1 100755 --- a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py @@ -23,8 +23,8 @@ class replica_bitcell_array_dummies_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() - factory.reset() debug.info(2, "Testing 7x5 replica array for 1rw cell with dummy row only") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py index d4b514df..8f091ada 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class replica_bitcell_array_leftrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py index 9127a934..1a4944bf 100755 --- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py @@ -23,8 +23,8 @@ class replica_bitcell_array_leftrbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() - factory.reset() debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) self.local_check(a) diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py index bc292041..be19330f 100755 --- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py @@ -23,6 +23,7 @@ class replica_bitcell_array_norbl_1rw_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 + openram.setup_bitcell() debug.info(2, "Testing 7x5 replica array for 1rw cell without replica column or dummy row") a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0]) diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py index c2f29c2f..8c32fb01 100755 --- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -31,6 +31,7 @@ class replica_bitcell_array_rightrbl_1rw_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args() diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py index 18ccb00c..6d3a73c5 100755 --- a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py @@ -31,6 +31,7 @@ class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test): openram.end_openram() + # run the test from the command line if __name__ == "__main__": (OPTS, args) = openram.parse_args()