From 8fd08916a1b6de6c2b417f37dc11c8ce9fd0f8dc Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 20 Oct 2022 15:16:10 -0700 Subject: [PATCH] Move is_non_inverting graph code to bitcell_base class to work with pbitcell too. --- compiler/modules/bitcell_1port.py | 4 ---- compiler/modules/bitcell_2port.py | 5 ----- compiler/modules/bitcell_base.py | 12 ++++++++++++ 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/compiler/modules/bitcell_1port.py b/compiler/modules/bitcell_1port.py index 57943697..a0fdf794 100644 --- a/compiler/modules/bitcell_1port.py +++ b/compiler/modules/bitcell_1port.py @@ -29,7 +29,3 @@ class bitcell_1port(bitcell_base): """ self.add_graph_edges(graph, port_nets) - def is_non_inverting(self): - """Return input to output polarity for module""" - - return False diff --git a/compiler/modules/bitcell_2port.py b/compiler/modules/bitcell_2port.py index 716c79b7..c346bad6 100644 --- a/compiler/modules/bitcell_2port.py +++ b/compiler/modules/bitcell_2port.py @@ -99,8 +99,3 @@ class bitcell_2port(bitcell_base): # Port 1 edges graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self) graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self) - - def is_non_inverting(self): - """Return input to output polarity for module""" - - return False diff --git a/compiler/modules/bitcell_base.py b/compiler/modules/bitcell_base.py index 25d3efe4..ca41725b 100644 --- a/compiler/modules/bitcell_base.py +++ b/compiler/modules/bitcell_base.py @@ -265,3 +265,15 @@ class bitcell_base(design): delay = math.sqrt(2*tstep*(vdd-spice["nom_threshold"])/m) return delay + + def build_graph(self, graph, inst_name, port_nets): + """ + Adds edges based on inputs/outputs. + Overrides base class function. + """ + debug.error("Must override build_graph function in bitcell base class.") + + def is_non_inverting(self): + """Return input to output polarity for module""" + + return False