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Fix cheat on wordline driver name.

This commit is contained in:
mrg 2021-11-03 11:53:30 -07:00
parent 6ee4697711
commit 8f296810be
1 changed files with 6 additions and 6 deletions
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12
technology/freepdk45/tech/freepdk45.lylvs
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@ -135,7 +135,7 @@ lv_ngate = ngate - vtg - thkox
gv_ngate = ngate & vtg - vth - thkox gv_ngate = ngate & vtg - vth - thkox
hv_ngate = ngate - vtg - vth & thkox hv_ngate = ngate - vtg - vth & thkox
cheat("cell_6t", "dummy_cell_6t", "cell_1rw", "dummy_cell_1rw", "cell_2rw", "dummy_cell_2rw", "dff","wordline_driver_0") { cheat("cell_6t", "dummy_cell_6t", "cell_1rw", "dummy_cell_1rw", "replica_cell_1rw", "cell_2rw", "dummy_cell_2rw", "replica_cell_2rw", "dff","wordline_driver*") {
# PMOS transistor device extraction # PMOS transistor device extraction
extract_devices(mos4("PMOS_VTL"), { "SD" => psd, "G" => lv_pgate, "tS" => psd, "tD" => psd, "tG" => poly, "W" => nwell }) extract_devices(mos4("PMOS_VTL"), { "SD" => psd, "G" => lv_pgate, "tS" => psd, "tD" => psd, "tG" => poly, "W" => nwell })
@ -206,13 +206,13 @@ connect(metal10, metal10_pin)
schematic.simplify schematic.simplify
if $connect_supplies if $connect_supplies
connect_implicit("vdd") connect_implicit("*", "vdd")
connect_implicit("gnd") connect_implicit("*", "gnd")
end end
#connect_global(pwell, "PWELL") connect_global(pwell, "PWELL")
#connect_global(nwell, "NWELL") connect_global(nwell, "NWELL")
#connect_global(bulk, "BULK") connect_global(bulk, "BULK")
for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*) for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*)
connect_explicit(pat, [ "NWELL", "vdd" ]) connect_explicit(pat, [ "NWELL", "vdd" ])