diff --git a/compiler/base/design.py b/compiler/base/design.py
index 43957cb6..f52aa100 100644
--- a/compiler/base/design.py
+++ b/compiler/base/design.py
@@ -65,8 +65,12 @@ class design(hierarchy_design):
         self.readwrite_ports = []
         # These are the read/write and write-only port indices
         self.write_ports = []
+        # These are the write-only port indices.
+        self.writeonly_ports = []
         # These are teh read/write and read-only port indice
         self.read_ports = []
+        # These are the read-only port indices.
+        self.readonly_ports = []
         # These are all the ports
         self.all_ports = list(range(total_ports))
         
@@ -78,9 +82,11 @@ class design(hierarchy_design):
             port_number += 1
         for port in range(OPTS.num_w_ports):
             self.write_ports.append(port_number)
+            self.writeonly_ports.append(port_number)            
             port_number += 1
         for port in range(OPTS.num_r_ports):
             self.read_ports.append(port_number)
+            self.readonly_ports.append(port_number)
             port_number += 1
 
     def analytical_power(self, proc, vdd, temp, load):
diff --git a/compiler/sram_base.py b/compiler/sram_base.py
index 879c4a04..29c3cbb9 100644
--- a/compiler/sram_base.py
+++ b/compiler/sram_base.py
@@ -226,12 +226,12 @@ class sram_base(design):
                                                            words_per_row=self.words_per_row,
                                                            port_type="rw")
             self.add_mod(self.control_logic_rw)
-        if len(self.write_ports)>0:
+        if len(self.writeonly_ports)>0:
             self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows,
                                                           words_per_row=self.words_per_row,
                                                           port_type="w")
             self.add_mod(self.control_logic_w)
-        if len(self.read_ports)>0:
+        if len(self.readonly_ports)>0:
             self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
                                                           words_per_row=self.words_per_row,
                                                           port_type="r")