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Replica bitcell with all the fixings

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This commit is contained in:
mrg
2020-08-11 15:00:29 -07:00
parent eef97ff215
commit 8e890c2014
6 changed files with 197 additions and 148 deletions
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compiler/modules/local_bitcell_array.py
+43 -12
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@@ -5,22 +5,22 @@
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import design
import bitcell_base_array
from globals import OPTS
from sram_factory import factory
from vector import vector
import debug
class local_bitcell_array(design.design):
class local_bitcell_array(bitcell_base_array.bitcell_base_array):
"""
A local bitcell array is a bitcell array with a wordline driver.
This can either be a single aray on its own if there is no hierarchical WL
or it can be combined into a larger array with hierarchical WL.
"""
def __init__(self, rows, cols, ports, left_rbl=0, right_rbl=0, name=""):
design.design.__init__(self, name)
debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,
self.num_words))
def __init__(self, rows, cols, ports, left_rbl=0, right_rbl=0, add_replica=True, name=""):
super().__init__(name, rows, cols, 0)
debug.info(2, "create local array of size {} rows x {} cols words".format(rows,
cols + left_rbl + right_rbl))
self.rows = rows
self.cols = cols
@@ -66,16 +66,47 @@ class local_bitcell_array(design.design):
self.add_mod(self.bitcell_array)
self.wl_array = factory.create(module_type="wordline_buffer_array",
rows=self.rows,
rows=self.rows + len(self.all_ports),
cols=self.cols)
self.add_mod(self.wl_array)
def add_pins(self):
self.bitline_names = self.bitcell_array.get_all_bitline_names()
self.add_pin_list(self.bitline_names, "INOUT")
self.wordline_names = self.bitcell_array.get_all_wordline_names()
self.add_pin_list(self.wordline_names, "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def create_instances(self):
""" Create the module instances used in this design """
self.wl_inst = self.add_inst(mod=self.wl_array)
self.connect_inst(self.pins)
internal_wl_names = [x + "i" for x in self.wordline_names]
self.wl_inst = self.add_inst(name="wl_driver",
mod=self.wl_array)
self.connect_inst(self.wordline_names + internal_wl_names + ["vdd", "gnd"])
self.array_inst = self.add_inst(mod=self.bitcell_array,
self.array_inst = self.add_inst(name="array",
mod=self.bitcell_array,
offset=self.wl_inst.lr())
self.connect_inst(self.pins)
self.connect_inst(self.bitline_names + internal_wl_names + ["vdd", "gnd"])
def place(self):
""" Place the bitcelll array to the right of the wl driver. """
self.wl_inst.place(vector(0, 0))
self.array_inst.place(self.wl_inst.lr())
self.height = self.bitcell_array.height
self.width = self.array_inst.rx()
def add_layout_pins(self):
for (x, y) in zip(self.bitline_names, self.bitcell_array.get_inouts()):
self.copy_layout_pin(self.array_inst, y, x)
for (x, y) in zip(self.wordline_names, self.wl_array.get_inputs()):
self.copy_layout_pin(self.wl_inst, y, x)