Merge branch 'super' into dev

compiler/base/channel_route.py

@@ -97,7 +97,7 @@ class channel_route(design.design):
         """
         name = "cr_{0}".format(channel_route.unique_id)
         channel_route.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         
         self.netlist = netlist
         self.offset = offset

compiler/base/contact.py

@@ -34,7 +34,7 @@ class contact(hierarchy_design.hierarchy_design):
         # This will ignore the name parameter since
         # we can guarantee a unique name here
         
-        hierarchy_design.hierarchy_design.__init__(self, name)
+        super().__init__(name)
         debug.info(4, "create contact object {0}".format(name))
 
         self.add_comment("layers: {0}".format(layer_stack))

compiler/base/design.py

@@ -20,7 +20,7 @@ class design(hierarchy_design):
     """
 
     def __init__(self, name):
-        hierarchy_design.__init__(self, name)
+        super().__init__(name)
         
         self.setup_drc_constants()
         self.setup_layer_constants()

compiler/base/geometry.py

@@ -160,7 +160,7 @@ class instance(geometry):
     """
     def __init__(self, name, mod, offset=[0, 0], mirror="R0", rotate=0):
         """Initializes an instance to represent a module"""
-        geometry.__init__(self)
+        super().__init__()
         debug.check(mirror not in ["R90", "R180", "R270"],
                     "Please use rotation and not mirroring during instantiation.")
 
@@ -284,7 +284,7 @@ class path(geometry):
 
     def __init__(self, lpp, coordinates, path_width):
         """Initializes a path for the specified layer"""
-        geometry.__init__(self)
+        super().__init__()
         self.name = "path"
         self.layerNumber = lpp[0]
         self.layerPurpose = lpp[1]
@@ -322,7 +322,7 @@ class label(geometry):
 
     def __init__(self, text, lpp, offset, zoom=-1):
         """Initializes a text label for specified layer"""
-        geometry.__init__(self)
+        super().__init__()
         self.name = "label"
         self.text = text
         self.layerNumber = lpp[0]
@@ -366,7 +366,7 @@ class rectangle(geometry):
 
     def __init__(self, lpp, offset, width, height):
         """Initializes a rectangular shape for specified layer"""
-        geometry.__init__(self)
+        super().__init__()
         self.name = "rect"
         self.layerNumber = lpp[0]
         self.layerPurpose = lpp[1]

compiler/base/route.py

@@ -30,7 +30,7 @@ class route(design):
     def __init__(self, obj, layer_stack, path, layer_widths=[None,1,None]):
         name = "route_{0}".format(route.unique_route_id)
         route.unique_route_id += 1
-        design.__init__(self, name)
+        super().__init__(name)
         debug.info(3, "create route obj {0}".format(name))
 
         self.obj = obj

compiler/characterizer/delay.py

@@ -41,7 +41,7 @@ class delay(simulation):
     """
 
     def __init__(self, sram, spfile, corner):
-        simulation.__init__(self, sram, spfile, corner)
+        super().__init__(sram, spfile, corner)
 
         self.targ_read_ports = []
         self.targ_write_ports = []

compiler/characterizer/functional.py

@@ -24,7 +24,7 @@ class functional(simulation):
     """
 
     def __init__(self, sram, spfile, corner):
-        simulation.__init__(self, sram, spfile, corner)
+        super().__init__(sram, spfile, corner)
         
         # Seed the characterizer with a constant seed for unit tests
         if OPTS.is_unit_test:

compiler/characterizer/model_check.py

@@ -26,7 +26,7 @@ class model_check(delay):
     """
 
     def __init__(self, sram, spfile, corner, custom_delaychain=False):
-        delay.__init__(self,sram,spfile,corner)
+        super().__init__(sram, spfile, corner)
         self.period = tech.spice["feasible_period"]
         self.create_data_names()
         self.custom_delaychain=custom_delaychain

compiler/modules/bank.py

@@ -36,7 +36,7 @@ class bank(design.design):
                 
         if name == "":
             name = "bank_{0}_{1}".format(self.word_size, self.num_words)
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,
                                                                       self.num_words))
         

compiler/modules/bank_select.py

@@ -24,7 +24,7 @@ class bank_select(design.design):
     """
 
     def __init__(self, name="bank_select", port="rw"):
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         self.port = port
         

compiler/modules/control_logic.py

@@ -23,7 +23,7 @@ class control_logic(design.design):
     def __init__(self, num_rows, words_per_row, word_size, spare_columns=None, sram=None, port_type="rw", name=""):
         """ Constructor """
         name = "control_logic_" + port_type
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(name))
         self.add_comment("num_rows: {0}".format(num_rows))
         self.add_comment("words_per_row: {0}".format(words_per_row))

compiler/modules/delay_chain.py

@@ -21,7 +21,7 @@ class delay_chain(design.design):
 
     def __init__(self, name, fanout_list):
         """init function"""
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "creating delay chain {0}".format(str(fanout_list)))
         self.add_comment("fanouts: {0}".format(str(fanout_list)))
         

compiler/modules/dff_array.py

@@ -24,7 +24,7 @@ class dff_array(design.design):
 
         if name=="":
             name = "dff_array_{0}x{1}".format(rows, columns)
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0} rows={1} cols={2}".format(self.name, self.rows, self.columns))
         self.add_comment("rows: {0} cols: {1}".format(rows, columns))
         

compiler/modules/dff_buf.py

@@ -27,7 +27,7 @@ class dff_buf(design.design):
         if name=="":
             name = "dff_buf_{0}".format(dff_buf.unique_id)
             dff_buf.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(self.name))
         self.add_comment("inv1: {0} inv2: {1}".format(inv1_size, inv2_size))
         

compiler/modules/dff_buf_array.py

@@ -27,7 +27,7 @@ class dff_buf_array(design.design):
         if name=="":
             name = "dff_buf_array_{0}x{1}_{2}".format(rows, columns, dff_buf_array.unique_id)
             dff_buf_array.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(self.name))
         self.add_comment("rows: {0} cols: {1}".format(rows, columns))
         self.add_comment("inv1: {0} inv2: {1}".format(inv1_size, inv2_size))

compiler/modules/dff_inv.py

@@ -25,7 +25,7 @@ class dff_inv(design.design):
         if name=="":
             name = "dff_inv_{0}".format(dff_inv.unique_id)
             dff_inv.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(self.name))
         self.add_comment("inv: {0}".format(inv_size))
 

compiler/modules/dff_inv_array.py

@@ -27,7 +27,7 @@ class dff_inv_array(design.design):
         if name=="":
             name = "dff_inv_array_{0}x{1}_{2}".format(rows, columns, dff_inv_array.unique_id)
             dff_inv_array.unique_id += 1
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {}".format(self.name))
         self.add_comment("rows: {0} cols: {1}".format(rows, columns))
         self.add_comment("inv1: {0}".format(inv1_size))

compiler/modules/hierarchical_decoder.py

@@ -18,7 +18,7 @@ class hierarchical_decoder(design.design):
     Dynamically generated hierarchical decoder.
     """
     def __init__(self, name, num_outputs):
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         self.AND_FORMAT = "DEC_AND_{0}"
         

compiler/modules/hierarchical_predecode.py

@@ -31,7 +31,7 @@ class hierarchical_predecode(design.design):
         self.column_decoder = (height != b.height)
             
         self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
-        design.design.__init__(self, name)
+        super().__init__(name)
     
     def add_pins(self):
         for k in range(self.number_of_inputs):

compiler/modules/hierarchical_predecode2x4.py

@@ -14,7 +14,7 @@ class hierarchical_predecode2x4(hierarchical_predecode):
     Pre 2x4 decoder used in hierarchical_decoder.
     """
     def __init__(self, name, height=None):
-        hierarchical_predecode.__init__(self, name, 2, height)
+        super().__init__( name, 2, height)
 
         self.create_netlist()
         if not OPTS.netlist_only:

compiler/modules/hierarchical_predecode3x8.py

@@ -14,7 +14,7 @@ class hierarchical_predecode3x8(hierarchical_predecode):
     Pre 3x8 decoder used in hierarchical_decoder.
     """
     def __init__(self, name, height=None):
-        hierarchical_predecode.__init__(self, name, 3, height)
+        super().__init__(name, 3, height)
 
         self.create_netlist()
         if not OPTS.netlist_only:

compiler/modules/hierarchical_predecode4x16.py

@@ -14,7 +14,7 @@ class hierarchical_predecode4x16(hierarchical_predecode):
     Pre 4x16 decoder used in hierarchical_decoder.
     """
     def __init__(self, name, height=None):
-        hierarchical_predecode.__init__(self, name, 4, height)
+        super().__init__(name, 4, height)
 
         self.create_netlist()
         if not OPTS.netlist_only:

compiler/modules/multibank.py

@@ -26,7 +26,7 @@ class multibank(design.design):
 
     def __init__(self, name, word_size, num_words, words_per_row, num_banks=1):
 
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2, "create sram of size {0} with {1} words".format(word_size,num_words))
 
         self.word_size = word_size

compiler/modules/port_address.py

@@ -25,7 +25,7 @@ class port_address(design.design):
         
         if name == "":
             name = "port_address_{0}_{1}".format(cols, rows)
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2, "create data port of cols {0} rows {1}".format(cols, rows))
 
         self.create_netlist()

compiler/modules/port_data.py

@@ -32,7 +32,7 @@ class port_data(design.design):
 
         if name == "":
             name = "port_data_{0}".format(self.port)
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2,
                    "create data port of size {0} with {1} words per row".format(self.word_size,
                                                                                    self.words_per_row))

compiler/modules/precharge_array.py

@@ -20,7 +20,7 @@ class precharge_array(design.design):
     """
 
     def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br", column_offset=0):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br))
         

compiler/modules/replica_column.py

@@ -22,7 +22,7 @@ class replica_column(design.design):
 
     def __init__(self, name, rows, left_rbl, right_rbl, replica_bit,
                  column_offset=0):
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         self.rows = rows
         self.left_rbl = left_rbl

compiler/modules/sense_amp.py

@@ -50,7 +50,7 @@ class sense_amp(design.design):
         return props.sense_amp.pin.en
 
     def __init__(self, name):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(2, "Create sense_amp")
 
         self.width = sense_amp.width

compiler/modules/sense_amp_array.py

@@ -22,7 +22,7 @@ class sense_amp_array(design.design):
 
     def __init__(self, name, word_size, words_per_row, num_spare_cols=None, column_offset=0):
 
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("word_size {0}".format(word_size))
         self.add_comment("words_per_row: {0}".format(words_per_row))

compiler/modules/single_level_column_mux_array.py

@@ -21,7 +21,7 @@ class single_level_column_mux_array(design.design):
     """
 
     def __init__(self, name, columns, word_size, bitcell_bl="bl", bitcell_br="br", column_offset=0):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br))
 

compiler/modules/tri_gate_array.py

@@ -19,7 +19,7 @@ class tri_gate_array(design.design):
 
     def __init__(self, columns, word_size, name):
         """Intial function of tri gate array """
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
 
         self.columns = columns

compiler/modules/wordline_driver_array.py

@@ -19,7 +19,7 @@ class wordline_driver_array(design.design):
     """
 
     def __init__(self, name, rows, cols):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("rows: {0} cols: {1}".format(rows, cols))
         

compiler/modules/write_driver_array.py

@@ -21,7 +21,7 @@ class write_driver_array(design.design):
 
     def __init__(self, name, columns, word_size, num_spare_cols=None, write_size=None, column_offset=0):
 
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("columns: {0}".format(columns))
         self.add_comment("word_size {0}".format(word_size))

compiler/modules/write_mask_and_array.py

@@ -19,7 +19,7 @@ class write_mask_and_array(design.design):
     """
 
     def __init__(self, name, columns, word_size, write_size, column_offset=0):
-        design.design.__init__(self, name)
+        super().__init__(name)
         debug.info(1, "Creating {0}".format(self.name))
         self.add_comment("columns: {0}".format(columns))
         self.add_comment("word_size {0}".format(word_size))

compiler/pgates/pand2.py

@@ -22,7 +22,7 @@ class pand2(pgate.pgate):
         self.vertical = vertical
         self.size = size
 
-        pgate.pgate.__init__(self, name, height, add_wells)
+        super().__init__(name, height, add_wells)
 
     def create_netlist(self):
         self.add_pins()

compiler/pgates/pand3.py

@@ -23,7 +23,7 @@ class pand3(pgate.pgate):
         self.size = size
         
         # Creates the netlist and layout
-        pgate.pgate.__init__(self, name, height, add_wells)
+        super().__init__(name, height, add_wells)
 
     def create_netlist(self):
         self.add_pins()

compiler/pgates/pbuf.py

@@ -25,7 +25,7 @@ class pbuf(pgate.pgate):
         self.height = height
 
         # Creates the netlist and layout
-        pgate.pgate.__init__(self, name, height)
+        super().__init__(name, height)
 
     def create_netlist(self):
         self.add_pins()

compiler/pgates/pdriver.py

@@ -35,7 +35,7 @@ class pdriver(pgate.pgate):
             debug.error("Cannot specify both size_list and inverting.", -1)
  
         # Creates the netlist and layout
-        pgate.pgate.__init__(self, name, height, add_wells)
+        super().__init__(name, height, add_wells)
         
     def compute_sizes(self):
         # size_list specified

compiler/pgates/pgate.py

@@ -26,7 +26,7 @@ class pgate(design.design):
 
     def __init__(self, name, height=None, add_wells=True):
         """ Creates a generic cell """
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         if height:
             self.height = height

compiler/pgates/pinv.py

@@ -44,7 +44,7 @@ class pinv(pgate.pgate):
         self.pmos_size = beta * size
         self.beta = beta
     
-        pgate.pgate.__init__(self, name, height, add_wells)
+        super().__init__(name, height, add_wells)
 
     def create_netlist(self):
         """ Calls all functions related to the generation of the netlist """

compiler/pgates/pinv_dec.py

@@ -38,7 +38,7 @@ class pinv_dec(pinv.pinv):
         else:
             self.supply_layer = "m2"
         
-        pinv.pinv.__init__(self, name, size, beta, self.cell_height, add_wells)
+        super().__init__(name, size, beta, self.cell_height, add_wells)
 
     def determine_tx_mults(self):
         """

compiler/pgates/pinvbuf.py

@@ -32,7 +32,7 @@ class pinvbuf(pgate.pgate):
         self.predriver_size = max(int(self.size / (self.stage_effort / 2)), 1)
 
         # Creates the netlist and layout
-        pgate.pgate.__init__(self, name)
+        super().__init__(name)
 
     def create_netlist(self):
         self.add_pins()

compiler/pgates/pnand2.py

@@ -43,7 +43,7 @@ class pnand2(pgate.pgate):
             self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
             
         # Creates the netlist and layout
-        pgate.pgate.__init__(self, name, height, add_wells)
+        super().__init__(name, height, add_wells)
    
     def create_netlist(self):
         self.add_pins()

compiler/pgates/pnand3.py

@@ -46,7 +46,7 @@ class pnand3(pgate.pgate):
             self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
 
         # Creates the netlist and layout
-        pgate.pgate.__init__(self, name, height, add_wells)
+        super().__init__(name, height, add_wells)
         
     def add_pins(self):
         """ Adds pins for spice netlist """

compiler/pgates/pnor2.py

@@ -42,7 +42,7 @@ class pnor2(pgate.pgate):
             self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
 
         # Creates the netlist and layout
-        pgate.pgate.__init__(self, name, height, add_wells)
+        super().__init__(name, height, add_wells)
         
     def create_netlist(self):
         self.add_pins()

compiler/pgates/precharge.py

@@ -23,7 +23,7 @@ class precharge(design.design):
     def __init__(self, name, size=1, bitcell_bl="bl", bitcell_br="br"):
 
         debug.info(2, "creating precharge cell {0}".format(name))
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         self.bitcell = factory.create(module_type="bitcell")
         self.beta = parameter["beta"]

compiler/pgates/ptristate_inv.py

@@ -38,7 +38,7 @@ class ptristate_inv(pgate.pgate):
         self.pmos_width = self.pmos_size * drc("minwidth_tx")
         
         # Creates the netlist and layout
-        pgate.pgate.__init__(self, name, height)
+        super().__init__(name, height)
 
     def create_netlist(self):
         """ Calls all functions related to the generation of the netlist """

compiler/pgates/ptx.py

@@ -75,7 +75,7 @@ class ptx(design.design):
         # replace periods with underscore for newer spice compatibility
         name = name.replace('.', '_')
         debug.info(3, "creating ptx {0}".format(name))
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         self.tx_type = tx_type
         self.mults = mults

compiler/pgates/pwrite_driver.py

@@ -22,7 +22,7 @@ class pwrite_driver(design.design):
     def __init__(self, name, size=0):
         debug.error("pwrite_driver not implemented yet.", -1)
         debug.info(1, "creating pwrite_driver {}".format(name))
-        design.design.__init__(self, name)
+        super().__init__(name)
         self.size = size
         self.beta = parameter["beta"]
         self.pmos_width = self.beta*self.size*parameter["min_tx_size"]

compiler/pgates/single_level_column_mux.py

@@ -30,7 +30,7 @@ class single_level_column_mux(pgate.pgate):
         self.bitcell_bl = bitcell_bl
         self.bitcell_br = bitcell_br
 
-        pgate.pgate.__init__(self, name)
+        super().__init__(name)
 
     def get_bl_names(self):
         return "bl"

compiler/pgates/wordline_driver.py

@@ -21,7 +21,7 @@ class wordline_driver(design.design):
     def __init__(self, name, size=1, height=None):
         debug.info(1, "Creating wordline_driver {}".format(name))
         self.add_comment("size: {}".format(size))
-        design.design.__init__(self, name)
+        super().__init__(name)
 
         if height is None:
             b = factory.create(module_type="bitcell")