From 30976df48f2f3346831f7b71c8d98f42977a144d Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 6 Aug 2020 11:33:26 -0700 Subject: [PATCH 1/4] Change inheritance inits to use super --- compiler/base/channel_route.py | 2 +- compiler/base/contact.py | 2 +- compiler/base/design.py | 2 +- compiler/base/geometry.py | 8 ++++---- compiler/base/route.py | 2 +- compiler/characterizer/delay.py | 2 +- compiler/characterizer/functional.py | 2 +- compiler/characterizer/measurements.py | 12 ++++++------ compiler/characterizer/model_check.py | 4 ++-- compiler/modules/bank.py | 2 +- compiler/modules/bank_select.py | 2 +- compiler/modules/control_logic.py | 2 +- compiler/modules/delay_chain.py | 2 +- compiler/modules/dff_array.py | 2 +- compiler/modules/dff_buf.py | 2 +- compiler/modules/dff_buf_array.py | 2 +- compiler/modules/dff_inv.py | 2 +- compiler/modules/dff_inv_array.py | 2 +- compiler/modules/hierarchical_decoder.py | 2 +- compiler/modules/hierarchical_predecode.py | 2 +- compiler/modules/hierarchical_predecode2x4.py | 2 +- compiler/modules/hierarchical_predecode3x8.py | 2 +- compiler/modules/hierarchical_predecode4x16.py | 2 +- compiler/modules/multibank.py | 2 +- compiler/modules/port_address.py | 2 +- compiler/modules/port_data.py | 2 +- compiler/modules/precharge_array.py | 2 +- compiler/modules/replica_column.py | 2 +- compiler/modules/sense_amp.py | 2 +- compiler/modules/sense_amp_array.py | 2 +- compiler/modules/single_level_column_mux_array.py | 2 +- compiler/modules/tri_gate_array.py | 2 +- compiler/modules/wordline_driver_array.py | 2 +- compiler/modules/write_driver_array.py | 2 +- compiler/modules/write_mask_and_array.py | 2 +- compiler/pgates/pand2.py | 2 +- compiler/pgates/pand3.py | 2 +- compiler/pgates/pbuf.py | 2 +- compiler/pgates/pdriver.py | 2 +- compiler/pgates/pgate.py | 2 +- compiler/pgates/pinv.py | 2 +- compiler/pgates/pinv_dec.py | 2 +- compiler/pgates/pinvbuf.py | 2 +- compiler/pgates/pnand2.py | 2 +- compiler/pgates/pnand3.py | 2 +- compiler/pgates/pnor2.py | 2 +- compiler/pgates/precharge.py | 2 +- compiler/pgates/ptristate_inv.py | 2 +- compiler/pgates/ptx.py | 2 +- compiler/pgates/pwrite_driver.py | 2 +- compiler/pgates/single_level_column_mux.py | 2 +- compiler/pgates/wordline_driver.py | 2 +- 52 files changed, 61 insertions(+), 61 deletions(-) diff --git a/compiler/base/channel_route.py b/compiler/base/channel_route.py index 00ad6e37..5ec955c1 100644 --- a/compiler/base/channel_route.py +++ b/compiler/base/channel_route.py @@ -97,7 +97,7 @@ class channel_route(design.design): """ name = "cr_{0}".format(channel_route.unique_id) channel_route.unique_id += 1 - design.design.__init__(self, name) + super().__init__(name) self.netlist = netlist self.offset = offset diff --git a/compiler/base/contact.py b/compiler/base/contact.py index cc1ca27a..16c671d4 100644 --- a/compiler/base/contact.py +++ b/compiler/base/contact.py @@ -34,7 +34,7 @@ class contact(hierarchy_design.hierarchy_design): # This will ignore the name parameter since # we can guarantee a unique name here - hierarchy_design.hierarchy_design.__init__(self, name) + super().__init__(name) debug.info(4, "create contact object {0}".format(name)) self.add_comment("layers: {0}".format(layer_stack)) diff --git a/compiler/base/design.py b/compiler/base/design.py index 2b2d7711..2a79120d 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -20,7 +20,7 @@ class design(hierarchy_design): """ def __init__(self, name): - hierarchy_design.__init__(self, name) + super().__init__(name) self.setup_drc_constants() self.setup_layer_constants() diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index 32af7ee9..171210ad 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -160,7 +160,7 @@ class instance(geometry): """ def __init__(self, name, mod, offset=[0, 0], mirror="R0", rotate=0): """Initializes an instance to represent a module""" - geometry.__init__(self) + super().__init__() debug.check(mirror not in ["R90", "R180", "R270"], "Please use rotation and not mirroring during instantiation.") @@ -284,7 +284,7 @@ class path(geometry): def __init__(self, lpp, coordinates, path_width): """Initializes a path for the specified layer""" - geometry.__init__(self) + super().__init__() self.name = "path" self.layerNumber = lpp[0] self.layerPurpose = lpp[1] @@ -322,7 +322,7 @@ class label(geometry): def __init__(self, text, lpp, offset, zoom=-1): """Initializes a text label for specified layer""" - geometry.__init__(self) + super().__init__() self.name = "label" self.text = text self.layerNumber = lpp[0] @@ -366,7 +366,7 @@ class rectangle(geometry): def __init__(self, lpp, offset, width, height): """Initializes a rectangular shape for specified layer""" - geometry.__init__(self) + super().__init__() self.name = "rect" self.layerNumber = lpp[0] self.layerPurpose = lpp[1] diff --git a/compiler/base/route.py b/compiler/base/route.py index c3e446a3..4e3d8a60 100644 --- a/compiler/base/route.py +++ b/compiler/base/route.py @@ -30,7 +30,7 @@ class route(design): def __init__(self, obj, layer_stack, path, layer_widths=[None,1,None]): name = "route_{0}".format(route.unique_route_id) route.unique_route_id += 1 - design.__init__(self, name) + super().__init__(name) debug.info(3, "create route obj {0}".format(name)) self.obj = obj diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 3f5d61af..54d6217c 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -41,7 +41,7 @@ class delay(simulation): """ def __init__(self, sram, spfile, corner): - simulation.__init__(self, sram, spfile, corner) + super().__init__(sram, spfile, corner) self.targ_read_ports = [] self.targ_write_ports = [] diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 2c391e38..8574c4f6 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -24,7 +24,7 @@ class functional(simulation): """ def __init__(self, sram, spfile, corner): - simulation.__init__(self, sram, spfile, corner) + super().__init__(sram, spfile, corner) # Seed the characterizer with a constant seed for unit tests if OPTS.is_unit_test: diff --git a/compiler/characterizer/measurements.py b/compiler/characterizer/measurements.py index 54f9973f..7d32c4f7 100644 --- a/compiler/characterizer/measurements.py +++ b/compiler/characterizer/measurements.py @@ -58,7 +58,7 @@ class delay_measure(spice_measurement): def __init__(self, measure_name, trig_name, targ_name, trig_dir_str, targ_dir_str,\ trig_vdd=0.5, targ_vdd=0.5, measure_scale=None, has_port=True): - spice_measurement.__init__(self, measure_name, measure_scale, has_port) + super().__init__(measure_name, measure_scale, has_port) self.set_meas_constants(trig_name, targ_name, trig_dir_str, targ_dir_str, trig_vdd, targ_vdd) def get_measure_function(self): @@ -95,7 +95,7 @@ class delay_measure(spice_measurement): class slew_measure(delay_measure): def __init__(self, measure_name, signal_name, slew_dir_str, measure_scale=None, has_port=True): - spice_measurement.__init__(self, measure_name, measure_scale, has_port) + super().__init__(measure_name, measure_scale, has_port) self.set_meas_constants(signal_name, slew_dir_str) def set_meas_constants(self, signal_name, slew_dir_str): @@ -120,7 +120,7 @@ class power_measure(spice_measurement): """Generates a spice measurement for the average power between two time points.""" def __init__(self, measure_name, power_type="", measure_scale=None, has_port=True): - spice_measurement.__init__(self, measure_name, measure_scale, has_port) + super().__init__(measure_name, measure_scale, has_port) self.set_meas_constants(power_type) def get_measure_function(self): @@ -144,7 +144,7 @@ class voltage_when_measure(spice_measurement): """Generates a spice measurement to measure the voltage of a signal based on the voltage of another.""" def __init__(self, measure_name, trig_name, targ_name, trig_dir_str, trig_vdd, measure_scale=None, has_port=True): - spice_measurement.__init__(self, measure_name, measure_scale, has_port) + super().__init__(measure_name, measure_scale, has_port) self.set_meas_constants(trig_name, targ_name, trig_dir_str, trig_vdd) def get_measure_function(self): @@ -177,7 +177,7 @@ class voltage_at_measure(spice_measurement): The time is considered variant with different periods.""" def __init__(self, measure_name, targ_name, measure_scale=None, has_port=True): - spice_measurement.__init__(self, measure_name, measure_scale, has_port) + super().__init__(measure_name, measure_scale, has_port) self.set_meas_constants(targ_name) def get_measure_function(self): @@ -198,4 +198,4 @@ class voltage_at_measure(spice_measurement): meas_name = self.name targ_name = self.targ_name_no_port return (meas_name,targ_name,time_at) - \ No newline at end of file + diff --git a/compiler/characterizer/model_check.py b/compiler/characterizer/model_check.py index b35c3c47..52100001 100644 --- a/compiler/characterizer/model_check.py +++ b/compiler/characterizer/model_check.py @@ -26,7 +26,7 @@ class model_check(delay): """ def __init__(self, sram, spfile, corner, custom_delaychain=False): - delay.__init__(self,sram,spfile,corner) + super().__init__(sram, spfile, corner) self.period = tech.spice["feasible_period"] self.create_data_names() self.custom_delaychain=custom_delaychain @@ -446,4 +446,4 @@ class model_check(delay): return name_dict - \ No newline at end of file + diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index b0707edb..cac1e278 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -36,7 +36,7 @@ class bank(design.design): if name == "": name = "bank_{0}_{1}".format(self.word_size, self.num_words) - design.design.__init__(self, name) + super().__init__(name) debug.info(2, "create sram of size {0} with {1} words".format(self.word_size, self.num_words)) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index b6246268..8a776d30 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -24,7 +24,7 @@ class bank_select(design.design): """ def __init__(self, name="bank_select", port="rw"): - design.design.__init__(self, name) + super().__init__(name) self.port = port diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index a4e26a6f..a17f5aa7 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -23,7 +23,7 @@ class control_logic(design.design): def __init__(self, num_rows, words_per_row, word_size, spare_columns=None, sram=None, port_type="rw", name=""): """ Constructor """ name = "control_logic_" + port_type - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {}".format(name)) self.add_comment("num_rows: {0}".format(num_rows)) self.add_comment("words_per_row: {0}".format(words_per_row)) diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index c261138a..246299c1 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -21,7 +21,7 @@ class delay_chain(design.design): def __init__(self, name, fanout_list): """init function""" - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "creating delay chain {0}".format(str(fanout_list))) self.add_comment("fanouts: {0}".format(str(fanout_list))) diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index d3f9b68e..c4f85a6d 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -24,7 +24,7 @@ class dff_array(design.design): if name=="": name = "dff_array_{0}x{1}".format(rows, columns) - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {0} rows={1} cols={2}".format(self.name, self.rows, self.columns)) self.add_comment("rows: {0} cols: {1}".format(rows, columns)) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index a1e54a4d..1657d7a8 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -27,7 +27,7 @@ class dff_buf(design.design): if name=="": name = "dff_buf_{0}".format(dff_buf.unique_id) dff_buf.unique_id += 1 - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {}".format(self.name)) self.add_comment("inv1: {0} inv2: {1}".format(inv1_size, inv2_size)) diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 1cbd9284..88852d45 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -27,7 +27,7 @@ class dff_buf_array(design.design): if name=="": name = "dff_buf_array_{0}x{1}_{2}".format(rows, columns, dff_buf_array.unique_id) dff_buf_array.unique_id += 1 - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {}".format(self.name)) self.add_comment("rows: {0} cols: {1}".format(rows, columns)) self.add_comment("inv1: {0} inv2: {1}".format(inv1_size, inv2_size)) diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index 9dcb84c5..033312ef 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -25,7 +25,7 @@ class dff_inv(design.design): if name=="": name = "dff_inv_{0}".format(dff_inv.unique_id) dff_inv.unique_id += 1 - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {}".format(self.name)) self.add_comment("inv: {0}".format(inv_size)) diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index aadb4257..6b08bcce 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -27,7 +27,7 @@ class dff_inv_array(design.design): if name=="": name = "dff_inv_array_{0}x{1}_{2}".format(rows, columns, dff_inv_array.unique_id) dff_inv_array.unique_id += 1 - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {}".format(self.name)) self.add_comment("rows: {0} cols: {1}".format(rows, columns)) self.add_comment("inv1: {0}".format(inv1_size)) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index dbacd051..e32fe1c6 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -18,7 +18,7 @@ class hierarchical_decoder(design.design): Dynamically generated hierarchical decoder. """ def __init__(self, name, num_outputs): - design.design.__init__(self, name) + super().__init__(name) self.AND_FORMAT = "DEC_AND_{0}" diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index a89f5fa6..9c34735d 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -31,7 +31,7 @@ class hierarchical_predecode(design.design): self.column_decoder = (height != b.height) self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) - design.design.__init__(self, name) + super().__init__(name) def add_pins(self): for k in range(self.number_of_inputs): diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index 9c7ddfa3..3c1daa6a 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -14,7 +14,7 @@ class hierarchical_predecode2x4(hierarchical_predecode): Pre 2x4 decoder used in hierarchical_decoder. """ def __init__(self, name, height=None): - hierarchical_predecode.__init__(self, name, 2, height) + super().__init__( name, 2, height) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index e8c44e48..7513ed7c 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -14,7 +14,7 @@ class hierarchical_predecode3x8(hierarchical_predecode): Pre 3x8 decoder used in hierarchical_decoder. """ def __init__(self, name, height=None): - hierarchical_predecode.__init__(self, name, 3, height) + super().__init__(name, 3, height) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/hierarchical_predecode4x16.py b/compiler/modules/hierarchical_predecode4x16.py index 4a258bfb..3b423fde 100644 --- a/compiler/modules/hierarchical_predecode4x16.py +++ b/compiler/modules/hierarchical_predecode4x16.py @@ -14,7 +14,7 @@ class hierarchical_predecode4x16(hierarchical_predecode): Pre 4x16 decoder used in hierarchical_decoder. """ def __init__(self, name, height=None): - hierarchical_predecode.__init__(self, name, 4, height) + super().__init__(name, 4, height) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/multibank.py b/compiler/modules/multibank.py index bf19954b..48bf5f1f 100644 --- a/compiler/modules/multibank.py +++ b/compiler/modules/multibank.py @@ -26,7 +26,7 @@ class multibank(design.design): def __init__(self, name, word_size, num_words, words_per_row, num_banks=1): - design.design.__init__(self, name) + super().__init__(name) debug.info(2, "create sram of size {0} with {1} words".format(word_size,num_words)) self.word_size = word_size diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 980c9d96..532463a7 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -25,7 +25,7 @@ class port_address(design.design): if name == "": name = "port_address_{0}_{1}".format(cols, rows) - design.design.__init__(self, name) + super().__init__(name) debug.info(2, "create data port of cols {0} rows {1}".format(cols, rows)) self.create_netlist() diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index bd6b39e2..eb827f2f 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -32,7 +32,7 @@ class port_data(design.design): if name == "": name = "port_data_{0}".format(self.port) - design.design.__init__(self, name) + super().__init__(name) debug.info(2, "create data port of size {0} with {1} words per row".format(self.word_size, self.words_per_row)) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index d37de64f..c2d3d986 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -20,7 +20,7 @@ class precharge_array(design.design): """ def __init__(self, name, columns, size=1, bitcell_bl="bl", bitcell_br="br", column_offset=0): - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("cols: {0} size: {1} bl: {2} br: {3}".format(columns, size, bitcell_bl, bitcell_br)) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 9613e6fa..31ca4180 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -22,7 +22,7 @@ class replica_column(design.design): def __init__(self, name, rows, left_rbl, right_rbl, replica_bit, column_offset=0): - design.design.__init__(self, name) + super().__init__(name) self.rows = rows self.left_rbl = left_rbl diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py index 35fbdf42..67703903 100644 --- a/compiler/modules/sense_amp.py +++ b/compiler/modules/sense_amp.py @@ -50,7 +50,7 @@ class sense_amp(design.design): return props.sense_amp.pin.en def __init__(self, name): - design.design.__init__(self, name) + super().__init__(name) debug.info(2, "Create sense_amp") self.width = sense_amp.width diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 98cbee66..20f6e06f 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -22,7 +22,7 @@ class sense_amp_array(design.design): def __init__(self, name, word_size, words_per_row, num_spare_cols=None, column_offset=0): - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("word_size {0}".format(word_size)) self.add_comment("words_per_row: {0}".format(words_per_row)) diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py index 8b01d111..f57bbb20 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/single_level_column_mux_array.py @@ -21,7 +21,7 @@ class single_level_column_mux_array(design.design): """ def __init__(self, name, columns, word_size, bitcell_bl="bl", bitcell_br="br", column_offset=0): - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br)) diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index e7ebd802..c329a04b 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -19,7 +19,7 @@ class tri_gate_array(design.design): def __init__(self, columns, word_size, name): """Intial function of tri gate array """ - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {0}".format(self.name)) self.columns = columns diff --git a/compiler/modules/wordline_driver_array.py b/compiler/modules/wordline_driver_array.py index e8a3c110..61f51404 100644 --- a/compiler/modules/wordline_driver_array.py +++ b/compiler/modules/wordline_driver_array.py @@ -19,7 +19,7 @@ class wordline_driver_array(design.design): """ def __init__(self, name, rows, cols): - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("rows: {0} cols: {1}".format(rows, cols)) diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index a6eb1384..665142ec 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -21,7 +21,7 @@ class write_driver_array(design.design): def __init__(self, name, columns, word_size, num_spare_cols=None, write_size=None, column_offset=0): - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) self.add_comment("word_size {0}".format(word_size)) diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index d48aefef..9b083512 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -19,7 +19,7 @@ class write_mask_and_array(design.design): """ def __init__(self, name, columns, word_size, write_size, column_offset=0): - design.design.__init__(self, name) + super().__init__(name) debug.info(1, "Creating {0}".format(self.name)) self.add_comment("columns: {0}".format(columns)) self.add_comment("word_size {0}".format(word_size)) diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 435ace1f..a46485d0 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -22,7 +22,7 @@ class pand2(pgate.pgate): self.vertical = vertical self.size = size - pgate.pgate.__init__(self, name, height, add_wells) + super().__init__(name, height, add_wells) def create_netlist(self): self.add_pins() diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index 92429921..72a57f74 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -23,7 +23,7 @@ class pand3(pgate.pgate): self.size = size # Creates the netlist and layout - pgate.pgate.__init__(self, name, height, add_wells) + super().__init__(name, height, add_wells) def create_netlist(self): self.add_pins() diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 8b9c4eab..d82e2091 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -25,7 +25,7 @@ class pbuf(pgate.pgate): self.height = height # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + super().__init__(name, height) def create_netlist(self): self.add_pins() diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 578a11c4..8916f0fa 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -35,7 +35,7 @@ class pdriver(pgate.pgate): debug.error("Cannot specify both size_list and inverting.", -1) # Creates the netlist and layout - pgate.pgate.__init__(self, name, height, add_wells) + super().__init__(name, height, add_wells) def compute_sizes(self): # size_list specified diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 1e55d5fb..57d93e6f 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -26,7 +26,7 @@ class pgate(design.design): def __init__(self, name, height=None, add_wells=True): """ Creates a generic cell """ - design.design.__init__(self, name) + super().__init__(, name) if height: self.height = height diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 4caf2a18..db46b6b1 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -44,7 +44,7 @@ class pinv(pgate.pgate): self.pmos_size = beta * size self.beta = beta - pgate.pgate.__init__(self, name, height, add_wells) + super().__init__(name, height, add_wells) def create_netlist(self): """ Calls all functions related to the generation of the netlist """ diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index 672bde2d..90c8e579 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -38,7 +38,7 @@ class pinv_dec(pinv.pinv): else: self.supply_layer = "m2" - pinv.pinv.__init__(self, name, size, beta, self.cell_height, add_wells) + super().__init__(, name, size, beta, self.cell_height, add_wells) def determine_tx_mults(self): """ diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 5b286e9b..f746736c 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -32,7 +32,7 @@ class pinvbuf(pgate.pgate): self.predriver_size = max(int(self.size / (self.stage_effort / 2)), 1) # Creates the netlist and layout - pgate.pgate.__init__(self, name) + super().__init__(name) def create_netlist(self): self.add_pins() diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index fb6bb210..c1295a1b 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -43,7 +43,7 @@ class pnand2(pgate.pgate): self.pmos_width = self.nearest_bin("pmos", self.pmos_width) # Creates the netlist and layout - pgate.pgate.__init__(self, name, height, add_wells) + super().__init__(name, height, add_wells) def create_netlist(self): self.add_pins() diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index e4e71e61..efcbe369 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -46,7 +46,7 @@ class pnand3(pgate.pgate): self.pmos_width = self.nearest_bin("pmos", self.pmos_width) # Creates the netlist and layout - pgate.pgate.__init__(self, name, height, add_wells) + super().__init__(name, height, add_wells) def add_pins(self): """ Adds pins for spice netlist """ diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index aad405e8..331a0745 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -42,7 +42,7 @@ class pnor2(pgate.pgate): self.pmos_width = self.nearest_bin("pmos", self.pmos_width) # Creates the netlist and layout - pgate.pgate.__init__(self, name, height, add_wells) + super().__init__(name, height, add_wells) def create_netlist(self): self.add_pins() diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 52d24390..d948056d 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -23,7 +23,7 @@ class precharge(design.design): def __init__(self, name, size=1, bitcell_bl="bl", bitcell_br="br"): debug.info(2, "creating precharge cell {0}".format(name)) - design.design.__init__(self, name) + super().__init__(, name) self.bitcell = factory.create(module_type="bitcell") self.beta = parameter["beta"] diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 9fd5f8b6..affc157e 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -38,7 +38,7 @@ class ptristate_inv(pgate.pgate): self.pmos_width = self.pmos_size * drc("minwidth_tx") # Creates the netlist and layout - pgate.pgate.__init__(self, name, height) + super().__init__(name, height) def create_netlist(self): """ Calls all functions related to the generation of the netlist """ diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index b6f839f3..6de86346 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -75,7 +75,7 @@ class ptx(design.design): # replace periods with underscore for newer spice compatibility name = name.replace('.', '_') debug.info(3, "creating ptx {0}".format(name)) - design.design.__init__(self, name) + super().__init__(, name) self.tx_type = tx_type self.mults = mults diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py index 87db7b20..2d091fd0 100644 --- a/compiler/pgates/pwrite_driver.py +++ b/compiler/pgates/pwrite_driver.py @@ -22,7 +22,7 @@ class pwrite_driver(design.design): def __init__(self, name, size=0): debug.error("pwrite_driver not implemented yet.", -1) debug.info(1, "creating pwrite_driver {}".format(name)) - design.design.__init__(self, name) + super().__init__(, name) self.size = size self.beta = parameter["beta"] self.pmos_width = self.beta*self.size*parameter["min_tx_size"] diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py index d2dbacc1..cd9be887 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/single_level_column_mux.py @@ -30,7 +30,7 @@ class single_level_column_mux(pgate.pgate): self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br - pgate.pgate.__init__(self, name) + super().__init__(name) def get_bl_names(self): return "bl" diff --git a/compiler/pgates/wordline_driver.py b/compiler/pgates/wordline_driver.py index c8cf1326..b8fa4631 100644 --- a/compiler/pgates/wordline_driver.py +++ b/compiler/pgates/wordline_driver.py @@ -21,7 +21,7 @@ class wordline_driver(design.design): def __init__(self, name, size=1, height=None): debug.info(1, "Creating wordline_driver {}".format(name)) self.add_comment("size: {}".format(size)) - design.design.__init__(self, name) + super().__init__(, name) if height is None: b = factory.create(module_type="bitcell") From 55814a8f74b43f3a7fe806da0718fd961f0929bb Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 12 Aug 2020 11:15:32 -0700 Subject: [PATCH 2/4] Fix syntax errors in pgates for super edits --- compiler/pgates/pgate.py | 2 +- compiler/pgates/precharge.py | 2 +- compiler/pgates/ptx.py | 2 +- compiler/pgates/pwrite_driver.py | 2 +- compiler/pgates/wordline_driver.py | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index 57d93e6f..082ef7b8 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -26,7 +26,7 @@ class pgate(design.design): def __init__(self, name, height=None, add_wells=True): """ Creates a generic cell """ - super().__init__(, name) + super().__init__(name) if height: self.height = height diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index d948056d..aefdbb86 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -23,7 +23,7 @@ class precharge(design.design): def __init__(self, name, size=1, bitcell_bl="bl", bitcell_br="br"): debug.info(2, "creating precharge cell {0}".format(name)) - super().__init__(, name) + super().__init__(name) self.bitcell = factory.create(module_type="bitcell") self.beta = parameter["beta"] diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 6de86346..1e4393e7 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -75,7 +75,7 @@ class ptx(design.design): # replace periods with underscore for newer spice compatibility name = name.replace('.', '_') debug.info(3, "creating ptx {0}".format(name)) - super().__init__(, name) + super().__init__(name) self.tx_type = tx_type self.mults = mults diff --git a/compiler/pgates/pwrite_driver.py b/compiler/pgates/pwrite_driver.py index 2d091fd0..6ae448f9 100644 --- a/compiler/pgates/pwrite_driver.py +++ b/compiler/pgates/pwrite_driver.py @@ -22,7 +22,7 @@ class pwrite_driver(design.design): def __init__(self, name, size=0): debug.error("pwrite_driver not implemented yet.", -1) debug.info(1, "creating pwrite_driver {}".format(name)) - super().__init__(, name) + super().__init__(name) self.size = size self.beta = parameter["beta"] self.pmos_width = self.beta*self.size*parameter["min_tx_size"] diff --git a/compiler/pgates/wordline_driver.py b/compiler/pgates/wordline_driver.py index b8fa4631..a8ca76f8 100644 --- a/compiler/pgates/wordline_driver.py +++ b/compiler/pgates/wordline_driver.py @@ -21,7 +21,7 @@ class wordline_driver(design.design): def __init__(self, name, size=1, height=None): debug.info(1, "Creating wordline_driver {}".format(name)) self.add_comment("size: {}".format(size)) - super().__init__(, name) + super().__init__(name) if height is None: b = factory.create(module_type="bitcell") From 15c8c200f3c2e3a0655d9ec11769818ba592c44d Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 12 Aug 2020 12:10:12 -0700 Subject: [PATCH 3/4] Undo super() in measurement abstract class --- compiler/characterizer/measurements.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/characterizer/measurements.py b/compiler/characterizer/measurements.py index 7d32c4f7..31da8ac5 100644 --- a/compiler/characterizer/measurements.py +++ b/compiler/characterizer/measurements.py @@ -58,7 +58,7 @@ class delay_measure(spice_measurement): def __init__(self, measure_name, trig_name, targ_name, trig_dir_str, targ_dir_str,\ trig_vdd=0.5, targ_vdd=0.5, measure_scale=None, has_port=True): - super().__init__(measure_name, measure_scale, has_port) + spice_measurement.__init__(self, measure_name, measure_scale, has_port) self.set_meas_constants(trig_name, targ_name, trig_dir_str, targ_dir_str, trig_vdd, targ_vdd) def get_measure_function(self): @@ -95,7 +95,7 @@ class delay_measure(spice_measurement): class slew_measure(delay_measure): def __init__(self, measure_name, signal_name, slew_dir_str, measure_scale=None, has_port=True): - super().__init__(measure_name, measure_scale, has_port) + spice_measurement.__init__(self, measure_name, measure_scale, has_port) self.set_meas_constants(signal_name, slew_dir_str) def set_meas_constants(self, signal_name, slew_dir_str): @@ -120,7 +120,7 @@ class power_measure(spice_measurement): """Generates a spice measurement for the average power between two time points.""" def __init__(self, measure_name, power_type="", measure_scale=None, has_port=True): - super().__init__(measure_name, measure_scale, has_port) + spice_measurement.__init__(self, measure_name, measure_scale, has_port) self.set_meas_constants(power_type) def get_measure_function(self): @@ -144,7 +144,7 @@ class voltage_when_measure(spice_measurement): """Generates a spice measurement to measure the voltage of a signal based on the voltage of another.""" def __init__(self, measure_name, trig_name, targ_name, trig_dir_str, trig_vdd, measure_scale=None, has_port=True): - super().__init__(measure_name, measure_scale, has_port) + spice_measurement.__init__(self, measure_name, measure_scale, has_port) self.set_meas_constants(trig_name, targ_name, trig_dir_str, trig_vdd) def get_measure_function(self): @@ -177,7 +177,7 @@ class voltage_at_measure(spice_measurement): The time is considered variant with different periods.""" def __init__(self, measure_name, targ_name, measure_scale=None, has_port=True): - super().__init__(measure_name, measure_scale, has_port) + spice_measurement.__init__(self, measure_name, measure_scale, has_port) self.set_meas_constants(targ_name) def get_measure_function(self): From 5fc643855365bcb157e8bfd06087ba30055c6d33 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 12 Aug 2020 13:22:28 -0700 Subject: [PATCH 4/4] Fix pinv_dec super call --- compiler/pgates/pinv_dec.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/pgates/pinv_dec.py b/compiler/pgates/pinv_dec.py index 90c8e579..458ce187 100644 --- a/compiler/pgates/pinv_dec.py +++ b/compiler/pgates/pinv_dec.py @@ -38,7 +38,7 @@ class pinv_dec(pinv.pinv): else: self.supply_layer = "m2" - super().__init__(, name, size, beta, self.cell_height, add_wells) + super().__init__(name, size, beta, self.cell_height, add_wells) def determine_tx_mults(self): """