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Merge branch 'super' into dev

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This commit is contained in:
mrg
2020-08-12 14:25:13 -07:00
parent 7ac4574e4f 5fc6438553
commit 8dbaa66aa5
52 changed files with 56 additions and 56 deletions
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compiler/pgates/pand2.py
+1 -1
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@@ -22,7 +22,7 @@ class pand2(pgate.pgate):
self.vertical = vertical
self.size = size
pgate.pgate.__init__(self, name, height, add_wells)
super().__init__(name, height, add_wells)
def create_netlist(self):
self.add_pins()
compiler/pgates/pand3.py
+1 -1
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@@ -23,7 +23,7 @@ class pand3(pgate.pgate):
self.size = size
# Creates the netlist and layout
pgate.pgate.__init__(self, name, height, add_wells)
super().__init__(name, height, add_wells)
def create_netlist(self):
self.add_pins()
compiler/pgates/pbuf.py
+1 -1
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@@ -25,7 +25,7 @@ class pbuf(pgate.pgate):
self.height = height
# Creates the netlist and layout
pgate.pgate.__init__(self, name, height)
super().__init__(name, height)
def create_netlist(self):
self.add_pins()
compiler/pgates/pdriver.py
+1 -1
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@@ -35,7 +35,7 @@ class pdriver(pgate.pgate):
debug.error("Cannot specify both size_list and inverting.", -1)
# Creates the netlist and layout
pgate.pgate.__init__(self, name, height, add_wells)
super().__init__(name, height, add_wells)
def compute_sizes(self):
# size_list specified
compiler/pgates/pgate.py
+1 -1
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@@ -26,7 +26,7 @@ class pgate(design.design):
def __init__(self, name, height=None, add_wells=True):
""" Creates a generic cell """
design.design.__init__(self, name)
super().__init__(name)
if height:
self.height = height
compiler/pgates/pinv.py
+1 -1
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@@ -44,7 +44,7 @@ class pinv(pgate.pgate):
self.pmos_size = beta * size
self.beta = beta
pgate.pgate.__init__(self, name, height, add_wells)
super().__init__(name, height, add_wells)
def create_netlist(self):
""" Calls all functions related to the generation of the netlist """
compiler/pgates/pinv_dec.py
+1 -1
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@@ -38,7 +38,7 @@ class pinv_dec(pinv.pinv):
else:
self.supply_layer = "m2"
pinv.pinv.__init__(self, name, size, beta, self.cell_height, add_wells)
super().__init__(name, size, beta, self.cell_height, add_wells)
def determine_tx_mults(self):
"""
compiler/pgates/pinvbuf.py
+1 -1
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@@ -32,7 +32,7 @@ class pinvbuf(pgate.pgate):
self.predriver_size = max(int(self.size / (self.stage_effort / 2)), 1)
# Creates the netlist and layout
pgate.pgate.__init__(self, name)
super().__init__(name)
def create_netlist(self):
self.add_pins()
compiler/pgates/pnand2.py
+1 -1
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@@ -43,7 +43,7 @@ class pnand2(pgate.pgate):
self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
# Creates the netlist and layout
pgate.pgate.__init__(self, name, height, add_wells)
super().__init__(name, height, add_wells)
def create_netlist(self):
self.add_pins()
compiler/pgates/pnand3.py
+1 -1
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@@ -46,7 +46,7 @@ class pnand3(pgate.pgate):
self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
# Creates the netlist and layout
pgate.pgate.__init__(self, name, height, add_wells)
super().__init__(name, height, add_wells)
def add_pins(self):
""" Adds pins for spice netlist """
compiler/pgates/pnor2.py
+1 -1
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@@ -42,7 +42,7 @@ class pnor2(pgate.pgate):
self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
# Creates the netlist and layout
pgate.pgate.__init__(self, name, height, add_wells)
super().__init__(name, height, add_wells)
def create_netlist(self):
self.add_pins()
compiler/pgates/precharge.py
+1 -1
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@@ -23,7 +23,7 @@ class precharge(design.design):
def __init__(self, name, size=1, bitcell_bl="bl", bitcell_br="br"):
debug.info(2, "creating precharge cell {0}".format(name))
design.design.__init__(self, name)
super().__init__(name)
self.bitcell = factory.create(module_type="bitcell")
self.beta = parameter["beta"]
compiler/pgates/ptristate_inv.py
+1 -1
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@@ -38,7 +38,7 @@ class ptristate_inv(pgate.pgate):
self.pmos_width = self.pmos_size * drc("minwidth_tx")
# Creates the netlist and layout
pgate.pgate.__init__(self, name, height)
super().__init__(name, height)
def create_netlist(self):
""" Calls all functions related to the generation of the netlist """
compiler/pgates/ptx.py
+1 -1
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@@ -75,7 +75,7 @@ class ptx(design.design):
# replace periods with underscore for newer spice compatibility
name = name.replace('.', '_')
debug.info(3, "creating ptx {0}".format(name))
design.design.__init__(self, name)
super().__init__(name)
self.tx_type = tx_type
self.mults = mults
compiler/pgates/pwrite_driver.py
+1 -1
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@@ -22,7 +22,7 @@ class pwrite_driver(design.design):
def __init__(self, name, size=0):
debug.error("pwrite_driver not implemented yet.", -1)
debug.info(1, "creating pwrite_driver {}".format(name))
design.design.__init__(self, name)
super().__init__(name)
self.size = size
self.beta = parameter["beta"]
self.pmos_width = self.beta*self.size*parameter["min_tx_size"]
compiler/pgates/single_level_column_mux.py
+1 -1
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@@ -30,7 +30,7 @@ class single_level_column_mux(pgate.pgate):
self.bitcell_bl = bitcell_bl
self.bitcell_br = bitcell_br
pgate.pgate.__init__(self, name)
super().__init__(name)
def get_bl_names(self):
return "bl"
compiler/pgates/wordline_driver.py
+1 -1
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@@ -21,7 +21,7 @@ class wordline_driver(design.design):
def __init__(self, name, size=1, height=None):
debug.info(1, "Creating wordline_driver {}".format(name))
self.add_comment("size: {}".format(size))
design.design.__init__(self, name)
super().__init__(name)
if height is None:
b = factory.create(module_type="bitcell")