Add dff_buf for buffered flop arrays.

compiler/modules/dff.py

@@ -10,7 +10,7 @@ class dff(design.design):
     Memory address flip-flop
     """
 
-    pin_names = ["d", "q", "clk", "vdd", "gnd"]
+    pin_names = ["D", "Q", "clk", "vdd", "gnd"]
     (width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"])
     

compiler/modules/dff_buf.py

@@ -0,0 +1,146 @@
+import debug
+import design
+from tech import drc
+from math import log
+from vector import vector
+from globals import OPTS
+from pinv import pinv
+
+class dff_buf(design.design):
+    """
+    This is a simple buffered DFF. The output is buffered
+    with two inverters, of variable size, to provide q
+    and qbar. This is to enable driving large fanout loads.
+    """
+
+    def __init__(self, inv1_size, inv2_size, name=""):
+
+        if name=="":
+            name = "dff_buf_{0}_{1}".format(inv1_size, inv2_size)
+        design.design.__init__(self, name)
+        debug.info(1, "Creating {}".format(self.name))
+
+        c = reload(__import__(OPTS.dff))
+        self.mod_dff = getattr(c, OPTS.dff)
+        self.dff = self.mod_dff("dff")
+        self.add_mod(self.dff)
+
+        self.inv1 = pinv(size=inv1_size,height=self.dff.height)
+        self.add_mod(self.inv1)
+
+        self.inv2 = pinv(size=inv2_size,height=self.dff.height)
+        self.add_mod(self.inv2)
+
+        self.width = self.dff.width + self.inv1.width + self.inv2.width
+        self.height = self.dff.height
+
+        self.create_layout()
+
+    def create_layout(self):
+        self.add_pins()
+        self.add_insts()
+        self.add_wires()
+        self.add_layout_pins()
+        self.DRC_LVS()
+        
+    def add_pins(self):
+        self.add_pin("D")
+        self.add_pin("Q")
+        self.add_pin("Qb")
+        self.add_pin("clk")
+        self.add_pin("vdd")
+        self.add_pin("gnd")
+
+    def add_insts(self):
+        # Add the DFF
+        self.dff_inst=self.add_inst(name="dff_buf_dff",
+                                    mod=self.dff,
+                                    offset=vector(0,0))
+        self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
+
+        # Add INV1 to the right
+        self.inv1_inst=self.add_inst(name="dff_buf_inv1",
+                                     mod=self.inv1,
+                                     offset=vector(self.dff_inst.rx(),0))
+        self.connect_inst(["qint", "Qb",  "vdd", "gnd"])
+        
+        # Add INV2 to the right
+        self.inv2_inst=self.add_inst(name="dff_buf_inv2",
+                                     mod=self.inv2,
+                                     offset=vector(self.inv1_inst.rx(),0))
+        self.connect_inst(["Qb", "Q",  "vdd", "gnd"])
+        
+    def add_wires(self):
+        # Route dff q to inv1 a
+        q_pin = self.dff_inst.get_pin("Q")
+        a1_pin = self.inv1_inst.get_pin("A")
+        mid_point = vector(a1_pin.cx(), q_pin.cy())
+        self.add_wire(("metal3","via2","metal2"),
+                      [q_pin.center(), mid_point, a1_pin.center()])
+        self.add_via_center(("metal2","via2","metal3"),
+                            q_pin.center())
+        self.add_via_center(("metal1","via1","metal2"),
+                            a1_pin.center())
+
+        # Route inv1 z to inv2 a
+        z1_pin = self.inv1_inst.get_pin("Z")
+        a2_pin = self.inv2_inst.get_pin("A")
+        mid_point = vector(z1_pin.cx(), a2_pin.cy())        
+        self.add_wire(("metal1","via1","metal2"),
+                      [z1_pin.center(), mid_point, a2_pin.center()])
+        
+    def add_layout_pins(self):
+
+        # Continous vdd rail along with label.
+        vdd_pin=self.dff_inst.get_pin("vdd")
+        self.add_layout_pin(text="vdd",
+                            layer="metal1",
+                            offset=vdd_pin.ll(),
+                            width=self.width,
+                            height=vdd_pin.height())
+
+        # Continous gnd rail along with label.
+        gnd_pin=self.dff_inst.get_pin("gnd")
+        self.add_layout_pin(text="gnd",
+                            layer="metal1",
+                            offset=gnd_pin.ll(),
+                            width=self.width,
+                            height=vdd_pin.height())
+            
+        clk_pin = self.dff_inst.get_pin("clk")
+        self.add_layout_pin(text="clk",
+                            layer=clk_pin.layer,
+                            offset=clk_pin.ll(),
+                            width=clk_pin.width(),
+                            height=clk_pin.height())
+
+        din_pin = self.dff_inst.get_pin("D")
+        self.add_layout_pin(text="D",
+                            layer=din_pin.layer,
+                            offset=din_pin.ll(),
+                            width=din_pin.width(),
+                            height=din_pin.height())
+
+        dout_pin = self.inv2_inst.get_pin("Z")
+        self.add_layout_pin(text="Q",
+                            layer=dout_pin.layer,
+                            offset=dout_pin.ll(),
+                            width=dout_pin.width(),
+                            height=dout_pin.height())
+
+        dout_pin = self.inv1_inst.get_pin("Z")
+        self.add_layout_pin(text="Qb",
+                            layer=dout_pin.layer,
+                            offset=dout_pin.ll(),
+                            width=dout_pin.width(),
+                            height=dout_pin.height())
+        
+        
+
+    def analytical_delay(self, slew, load=0.0):
+        """ Calculate the analytical delay of DFF-> INV -> INV """
+        dff_delay=self.dff.analytical_delay(slew=slew, load=self.inv1.input_load())
+        inv1_delay = self.inv1.analytical_delay(slew=dff_delay.slew, load=self.inv2.input_load()) 
+        inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load)
+        return dff_delay + inv1_delay + inv2_delay
+            

compiler/tests/11_dff_buf_test.py

@@ -0,0 +1,36 @@
+#!/usr/bin/env python2.7
+"""
+Run a regresion test on a dff_buf.
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+class dff_buf_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        global verify
+        import verify
+        OPTS.check_lvsdrc = False
+
+        import dff_buf
+
+        debug.info(2, "Testing dff_buf 4x 8x")
+        a = dff_buf.dff_buf(4, 8)
+        self.local_check(a)
+
+        OPTS.check_lvsdrc = True
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()