diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py
index 2db12281..62e424cb 100644
--- a/compiler/modules/dff.py
+++ b/compiler/modules/dff.py
@@ -10,7 +10,7 @@ class dff(design.design):
     Memory address flip-flop
     """
 
-    pin_names = ["d", "q", "clk", "vdd", "gnd"]
+    pin_names = ["D", "Q", "clk", "vdd", "gnd"]
     (width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"], layer["boundary"])
     
diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py
new file mode 100644
index 00000000..bcd03f16
--- /dev/null
+++ b/compiler/modules/dff_buf.py
@@ -0,0 +1,146 @@
+import debug
+import design
+from tech import drc
+from math import log
+from vector import vector
+from globals import OPTS
+from pinv import pinv
+
+class dff_buf(design.design):
+    """
+    This is a simple buffered DFF. The output is buffered
+    with two inverters, of variable size, to provide q
+    and qbar. This is to enable driving large fanout loads.
+    """
+
+    def __init__(self, inv1_size, inv2_size, name=""):
+
+        if name=="":
+            name = "dff_buf_{0}_{1}".format(inv1_size, inv2_size)
+        design.design.__init__(self, name)
+        debug.info(1, "Creating {}".format(self.name))
+
+        c = reload(__import__(OPTS.dff))
+        self.mod_dff = getattr(c, OPTS.dff)
+        self.dff = self.mod_dff("dff")
+        self.add_mod(self.dff)
+
+        self.inv1 = pinv(size=inv1_size,height=self.dff.height)
+        self.add_mod(self.inv1)
+
+        self.inv2 = pinv(size=inv2_size,height=self.dff.height)
+        self.add_mod(self.inv2)
+
+        self.width = self.dff.width + self.inv1.width + self.inv2.width
+        self.height = self.dff.height
+
+        self.create_layout()
+
+    def create_layout(self):
+        self.add_pins()
+        self.add_insts()
+        self.add_wires()
+        self.add_layout_pins()
+        self.DRC_LVS()
+        
+    def add_pins(self):
+        self.add_pin("D")
+        self.add_pin("Q")
+        self.add_pin("Qb")
+        self.add_pin("clk")
+        self.add_pin("vdd")
+        self.add_pin("gnd")
+
+    def add_insts(self):
+        # Add the DFF
+        self.dff_inst=self.add_inst(name="dff_buf_dff",
+                                    mod=self.dff,
+                                    offset=vector(0,0))
+        self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
+
+        # Add INV1 to the right
+        self.inv1_inst=self.add_inst(name="dff_buf_inv1",
+                                     mod=self.inv1,
+                                     offset=vector(self.dff_inst.rx(),0))
+        self.connect_inst(["qint", "Qb",  "vdd", "gnd"])
+        
+        # Add INV2 to the right
+        self.inv2_inst=self.add_inst(name="dff_buf_inv2",
+                                     mod=self.inv2,
+                                     offset=vector(self.inv1_inst.rx(),0))
+        self.connect_inst(["Qb", "Q",  "vdd", "gnd"])
+        
+    def add_wires(self):
+        # Route dff q to inv1 a
+        q_pin = self.dff_inst.get_pin("Q")
+        a1_pin = self.inv1_inst.get_pin("A")
+        mid_point = vector(a1_pin.cx(), q_pin.cy())
+        self.add_wire(("metal3","via2","metal2"),
+                      [q_pin.center(), mid_point, a1_pin.center()])
+        self.add_via_center(("metal2","via2","metal3"),
+                            q_pin.center())
+        self.add_via_center(("metal1","via1","metal2"),
+                            a1_pin.center())
+
+        # Route inv1 z to inv2 a
+        z1_pin = self.inv1_inst.get_pin("Z")
+        a2_pin = self.inv2_inst.get_pin("A")
+        mid_point = vector(z1_pin.cx(), a2_pin.cy())        
+        self.add_wire(("metal1","via1","metal2"),
+                      [z1_pin.center(), mid_point, a2_pin.center()])
+        
+    def add_layout_pins(self):
+
+        # Continous vdd rail along with label.
+        vdd_pin=self.dff_inst.get_pin("vdd")
+        self.add_layout_pin(text="vdd",
+                            layer="metal1",
+                            offset=vdd_pin.ll(),
+                            width=self.width,
+                            height=vdd_pin.height())
+
+        # Continous gnd rail along with label.
+        gnd_pin=self.dff_inst.get_pin("gnd")
+        self.add_layout_pin(text="gnd",
+                            layer="metal1",
+                            offset=gnd_pin.ll(),
+                            width=self.width,
+                            height=vdd_pin.height())
+            
+        clk_pin = self.dff_inst.get_pin("clk")
+        self.add_layout_pin(text="clk",
+                            layer=clk_pin.layer,
+                            offset=clk_pin.ll(),
+                            width=clk_pin.width(),
+                            height=clk_pin.height())
+
+        din_pin = self.dff_inst.get_pin("D")
+        self.add_layout_pin(text="D",
+                            layer=din_pin.layer,
+                            offset=din_pin.ll(),
+                            width=din_pin.width(),
+                            height=din_pin.height())
+
+        dout_pin = self.inv2_inst.get_pin("Z")
+        self.add_layout_pin(text="Q",
+                            layer=dout_pin.layer,
+                            offset=dout_pin.ll(),
+                            width=dout_pin.width(),
+                            height=dout_pin.height())
+
+        dout_pin = self.inv1_inst.get_pin("Z")
+        self.add_layout_pin(text="Qb",
+                            layer=dout_pin.layer,
+                            offset=dout_pin.ll(),
+                            width=dout_pin.width(),
+                            height=dout_pin.height())
+        
+        
+
+    def analytical_delay(self, slew, load=0.0):
+        """ Calculate the analytical delay of DFF-> INV -> INV """
+        dff_delay=self.dff.analytical_delay(slew=slew, load=self.inv1.input_load())
+        inv1_delay = self.inv1.analytical_delay(slew=dff_delay.slew, load=self.inv2.input_load()) 
+        inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load)
+        return dff_delay + inv1_delay + inv2_delay
+            
diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py
new file mode 100644
index 00000000..3827647e
--- /dev/null
+++ b/compiler/tests/11_dff_buf_test.py
@@ -0,0 +1,36 @@
+#!/usr/bin/env python2.7
+"""
+Run a regresion test on a dff_buf.
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+class dff_buf_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        global verify
+        import verify
+        OPTS.check_lvsdrc = False
+
+        import dff_buf
+
+        debug.info(2, "Testing dff_buf 4x 8x")
+        a = dff_buf.dff_buf(4, 8)
+        self.local_check(a)
+
+        OPTS.check_lvsdrc = True
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()
diff --git a/technology/freepdk45/gds_lib/dff.gds b/technology/freepdk45/gds_lib/dff.gds
index 57202026..db7d3af3 100644
Binary files a/technology/freepdk45/gds_lib/dff.gds and b/technology/freepdk45/gds_lib/dff.gds differ
diff --git a/technology/freepdk45/sp_lib/dff.sp b/technology/freepdk45/sp_lib/dff.sp
index 8cc62891..51d99ad1 100644
--- a/technology/freepdk45/sp_lib/dff.sp
+++ b/technology/freepdk45/sp_lib/dff.sp
@@ -3,11 +3,11 @@
 * Program "Calibre xRC"
 * Version "v2007.2_34.24"
 * 
-.subckt dff d q clk vdd gnd
+.subckt dff D Q clk vdd gnd
 * 
-MM21 q a_66_6# gnd gnd NMOS_VTG L=5e-08 W=5e-07
+MM21 Q a_66_6# gnd gnd NMOS_VTG L=5e-08 W=5e-07
 MM19 a_76_6# a_2_6# a_66_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
-MM20 gnd q a_76_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM20 gnd Q a_76_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
 MM18 a_66_6# clk a_61_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
 MM17 a_61_6# a_34_4# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
 MM10 gnd clk a_2_6# gnd NMOS_VTG L=5e-08 W=5e-07
@@ -15,9 +15,9 @@ MM16 a_34_4# a_22_6# gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
 MM15 gnd a_34_4# a_31_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
 MM14 a_31_6# clk a_22_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
 MM13 a_22_6# a_2_6# a_17_6# gnd NMOS_VTG L=5e-08 W=2.5e-07
-MM12 a_17_6# d gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
-MM11 q a_66_6# vdd vdd PMOS_VTG L=5e-08 W=1e-06
-MM9 vdd q a_76_84# vdd PMOS_VTG L=5e-08 W=2.5e-07
+MM12 a_17_6# D gnd gnd NMOS_VTG L=5e-08 W=2.5e-07
+MM11 Q a_66_6# vdd vdd PMOS_VTG L=5e-08 W=1e-06
+MM9 vdd Q a_76_84# vdd PMOS_VTG L=5e-08 W=2.5e-07
 MM8 a_76_84# clk a_66_6# vdd PMOS_VTG L=5e-08 W=2.5e-07
 MM7 a_66_6# a_2_6# a_61_74# vdd PMOS_VTG L=5e-08 W=5e-07
 MM6 a_61_74# a_34_4# vdd vdd PMOS_VTG L=5e-08 W=5e-07
@@ -26,16 +26,16 @@ MM5 a_34_4# a_22_6# vdd vdd PMOS_VTG L=5e-08 W=5e-07
 MM4 vdd a_34_4# a_31_74# vdd PMOS_VTG L=5e-08 W=5e-07
 MM3 a_31_74# a_2_6# a_22_6# vdd PMOS_VTG L=5e-08 W=5e-07
 MM2 a_22_6# clk a_17_74# vdd PMOS_VTG L=5e-08 W=5e-07
-MM1 a_17_74# d vdd vdd PMOS_VTG L=5e-08 W=5e-07
+MM1 a_17_74# D vdd vdd PMOS_VTG L=5e-08 W=5e-07
 * c_9 a_66_6# 0 0.271997f
 * c_20 clk 0 0.350944f
-* c_27 q 0 0.202617f
+* c_27 Q 0 0.202617f
 * c_32 a_76_84# 0 0.0210573f
 * c_38 a_76_6# 0 0.0204911f
 * c_45 a_34_4# 0 0.172306f
 * c_55 a_2_6# 0 0.283119f
 * c_59 a_22_6# 0 0.157312f
-* c_64 d 0 0.0816386f
+* c_64 D 0 0.0816386f
 * c_73 gnd 0 0.254131f
 * c_81 vdd 0 0.23624f
 *
diff --git a/technology/scn3me_subm/gds_lib/dff.gds b/technology/scn3me_subm/gds_lib/dff.gds
index 679792f4..b96235c7 100644
Binary files a/technology/scn3me_subm/gds_lib/dff.gds and b/technology/scn3me_subm/gds_lib/dff.gds differ
diff --git a/technology/scn3me_subm/mag_lib/dff.mag b/technology/scn3me_subm/mag_lib/dff.mag
index a0f5e0b0..19825153 100644
--- a/technology/scn3me_subm/mag_lib/dff.mag
+++ b/technology/scn3me_subm/mag_lib/dff.mag
@@ -1,299 +1,279 @@
 magic
 tech scmos
-timestamp 1518655545
+timestamp 1518823399
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+rect 39 19 43 23
+rect 53 67 57 71
+rect 59 59 63 63
+rect 74 61 78 65
+rect 59 33 63 37
+rect 77 47 81 51
+rect 85 41 89 45
+rect 79 27 83 31
+<< metal1 >>
+rect 0 97 109 103
+rect 14 94 18 97
+rect 6 93 10 94
+rect 28 93 32 94
+rect 22 74 28 77
+rect 42 93 46 97
+rect 50 93 54 94
+rect 58 93 62 97
+rect 71 93 77 94
+rect 71 74 72 93
+rect 76 74 77 93
+rect 86 93 90 97
+rect 50 71 53 74
+rect 43 68 53 71
+rect 26 57 45 60
+rect 52 60 59 63
+rect 52 54 55 60
+rect 71 56 74 65
+rect 10 50 31 52
+rect 35 51 55 54
+rect 62 53 74 56
+rect 94 93 98 94
+rect 102 93 106 97
+rect 6 49 34 50
+rect 21 43 38 46
+rect 18 34 25 37
+rect 62 37 65 53
+rect 94 51 98 54
+rect 81 48 94 51
+rect 74 41 85 44
+rect 29 34 59 37
+rect 6 25 10 26
+rect 14 25 18 26
+rect 31 23 34 34
+rect 63 34 65 37
+rect 94 31 98 47
+rect 83 28 98 31
+rect 94 25 98 28
+rect 43 19 53 22
+rect 50 16 53 19
+rect 22 15 32 16
+rect 22 13 28 15
+rect 41 15 46 16
+rect 45 6 46 15
+rect 50 15 54 16
+rect 58 15 62 16
+rect 70 15 77 16
+rect 70 13 72 15
+rect 71 6 72 13
+rect 76 6 77 15
+rect 14 3 18 6
+rect 41 3 46 6
+rect 58 3 62 6
+rect 86 3 90 6
+rect 102 3 106 6
+rect 0 -3 109 3
+<< m2contact >>
+rect 22 70 26 74
+rect 70 70 74 74
+rect 22 57 26 61
+rect 6 50 10 54
+rect 38 43 42 47
+rect 14 33 18 37
+rect 94 47 98 51
+rect 70 40 74 44
+rect 6 26 10 30
+rect 22 16 26 20
+rect 70 16 74 20
 << metal2 >>
-rect 18 61 22 70
-rect 2 30 6 50
-rect 18 20 22 57
-rect 66 44 70 70
-rect 66 20 70 40
+rect 22 61 26 70
+rect 6 30 10 50
+rect 22 20 26 57
+rect 70 44 74 70
+rect 70 20 74 40
 << m3p >>
-rect -2 0 98 100
+rect 0 0 109 100
 << labels >>
-rlabel metal1 23 100 23 100 5 vdd
-rlabel metal1 38 -1 38 -1 1 gnd
-rlabel m2contact 11 34 11 34 1 clk
-rlabel m2contact 36 45 36 45 1 d
-rlabel m2contact 91 49 91 49 1 q
+rlabel m2contact 15 34 15 34 4 clk
+rlabel m2contact 40 45 40 45 4 D
+rlabel m2contact 96 49 96 49 4 Q
+rlabel metal1 32 98 32 98 4 vdd
+rlabel metal1 44 1 44 1 4 gnd
+<< properties >>
+string path 0.000 0.000 900.000 0.000 900.000 900.000 0.000 900.000 0.000 0.000 
 << end >>
diff --git a/technology/scn3me_subm/sp_lib/dff.sp b/technology/scn3me_subm/sp_lib/dff.sp
index 6d57e652..61515ab6 100644
--- a/technology/scn3me_subm/sp_lib/dff.sp
+++ b/technology/scn3me_subm/sp_lib/dff.sp
@@ -1,8 +1,8 @@
 * Positive edge-triggered FF
-.subckt dff d q clk vdd gnd
+.subckt dff D Q clk vdd gnd
 M0 vdd clk a_2_6# vdd p w=12u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
-M1 a_17_74# d vdd vdd p w=6u l=0.6u
+M1 a_17_74# D vdd vdd p w=6u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
 M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
@@ -18,13 +18,13 @@ M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
 M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
-M9 vdd q a_76_84# vdd p w=3u l=0.6u
+M9 vdd Q a_76_84# vdd p w=3u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
 M10 gnd clk a_2_6# gnd n w=6u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
-M11 q a_66_6# vdd vdd p w=12u l=0.6u
+M11 Q a_66_6# vdd vdd p w=12u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
-M12 a_17_6# d gnd gnd n w=3u l=0.6u
+M12 a_17_6# D gnd gnd n w=3u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
 M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
@@ -40,8 +40,8 @@ M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
 M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
-M20 gnd q a_76_6# gnd n w=3u l=0.6u
+M20 gnd Q a_76_6# gnd n w=3u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
-M21 q a_66_6# gnd gnd n w=6u l=0.6u
+M21 Q a_66_6# gnd gnd n w=6u l=0.6u
 + ad=0p pd=0u as=0p ps=0u 
 .ends dff