From 8d5db500626acb1d2146e453a900251bf9fd7eab Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 8 Oct 2020 16:40:53 -0700 Subject: [PATCH] Fix missing update for left RBL offset --- compiler/modules/replica_bitcell_array.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 4e58393c..3a4a9011 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -440,7 +440,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): else: offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - (self.col_end_offset.y/self.cell.height)) + self.strap_offset.scale(bit, -self.rbl[0] - 1) - self.replica_col_insts[len(self.left_rbl) + bit].place(offset) + self.replica_col_insts[self.rbl[0] + bit].place(offset) # Replica dummy rows # Add the dummy rows even if we aren't adding the replica column to this bitcell array