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Use OPTS.bitcell everywhere

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This commit is contained in:
mrg
2020-11-05 16:55:08 -08:00
parent 18d2987805
commit 8be1436d51
17 changed files with 21 additions and 20 deletions
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compiler/modules/port_data.py
+3 -3
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@@ -33,7 +33,7 @@ class port_data(design.design):
self.num_spare_cols = 0
if not bit_offsets:
bitcell = factory.create(module_type="bitcell")
bitcell = factory.create(module_type=OPTS.bitcell)
self.bit_offsets = []
for i in range(self.num_cols + self.num_spare_cols):
self.bit_offsets.append(i * bitcell.width)
@@ -191,7 +191,7 @@ class port_data(design.design):
# and mirroring happens correctly
# Used for names/dimensions only
self.cell = factory.create(module_type="bitcell")
self.cell = factory.create(module_type=OPTS.bitcell)
if self.port == 0:
# Append an offset on the left
@@ -270,7 +270,7 @@ class port_data(design.design):
# create arrays of bitline and bitline_bar names for read,
# write, or all ports
self.bitcell = factory.create(module_type="bitcell")
self.bitcell = factory.create(module_type=OPTS.bitcell)
self.bl_names = self.bitcell.get_all_bl_names()
self.br_names = self.bitcell.get_all_br_names()
self.wl_names = self.bitcell.get_all_wl_names()