From 8be1436d51c6004e29f6b8486eb51574fc2e7dbc Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 5 Nov 2020 16:55:08 -0800 Subject: [PATCH] Use OPTS.bitcell everywhere --- compiler/modules/bitcell_array.py | 2 +- compiler/modules/bitcell_base_array.py | 3 ++- compiler/modules/col_cap_array.py | 2 +- compiler/modules/dummy_array.py | 4 ++-- compiler/modules/hierarchical_decoder.py | 2 +- compiler/modules/hierarchical_predecode.py | 2 +- compiler/modules/local_bitcell_array.py | 2 +- compiler/modules/orig_bitcell_array.py | 2 +- compiler/modules/port_address.py | 2 +- compiler/modules/port_data.py | 6 +++--- compiler/modules/replica_bitcell_array.py | 2 +- compiler/modules/replica_column.py | 2 +- compiler/modules/row_cap_array.py | 2 +- compiler/modules/sense_amp_array.py | 2 +- compiler/modules/wordline_buffer_array.py | 2 +- compiler/modules/write_driver_array.py | 2 +- compiler/modules/write_mask_and_array.py | 2 +- 17 files changed, 21 insertions(+), 20 deletions(-) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index f586e9ed..10abe1e2 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -52,7 +52,7 @@ class bitcell_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) self.add_mod(self.cell) def create_instances(self): diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 86ee5d43..b1ee88a4 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -9,6 +9,7 @@ import debug import design from tech import cell_properties from sram_factory import factory +from globals import OPTS class bitcell_base_array(design.design): @@ -24,7 +25,7 @@ class bitcell_base_array(design.design): self.column_offset = column_offset # Bitcell for port names only - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) self.wordline_names = [[] for port in self.all_ports] self.all_wordline_names = [] diff --git a/compiler/modules/col_cap_array.py b/compiler/modules/col_cap_array.py index 8aaff142..ffbf6413 100644 --- a/compiler/modules/col_cap_array.py +++ b/compiler/modules/col_cap_array.py @@ -51,7 +51,7 @@ class col_cap_array(bitcell_base_array): self.dummy_cell = factory.create(module_type="col_cap_{}".format(OPTS.bitcell)) self.add_mod(self.dummy_cell) - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) def create_instances(self): """ Create the module instances used in this design """ diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 6368f9c8..51b423ae 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -44,8 +44,8 @@ class dummy_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell)) - self.cell = factory.create(module_type="bitcell") + self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell) + self.cell = factory.create(module_type=OPTS.bitcell) self.add_mod(self.dummy_cell) def create_instances(self): diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index c121f53a..372e9792 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -27,7 +27,7 @@ class hierarchical_decoder(design.design): self.pre3x8_inst = [] self.pre4x16_inst = [] - b = factory.create(module_type="bitcell") + b = factory.create(module_type=OPTS.bitcell) self.cell_height = b.height self.num_outputs = num_outputs diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index ea1f1215..9b5cab65 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -21,7 +21,7 @@ class hierarchical_predecode(design.design): def __init__(self, name, input_number, height=None): self.number_of_inputs = input_number - b = factory.create(module_type="bitcell") + b = factory.create(module_type=OPTS.bitcell) if not height: self.cell_height = b.height diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index b4702b2c..5ff91268 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -64,7 +64,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ # This is just used for names - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) self.bitcell_array = factory.create(module_type="replica_bitcell_array", cols=self.cols, diff --git a/compiler/modules/orig_bitcell_array.py b/compiler/modules/orig_bitcell_array.py index cf982ce5..3391a470 100644 --- a/compiler/modules/orig_bitcell_array.py +++ b/compiler/modules/orig_bitcell_array.py @@ -46,7 +46,7 @@ class bitcell_array(bitcell_base_array): def add_modules(self): """ Add the modules used in this design """ - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) self.add_mod(self.cell) def create_instances(self): diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index 48140995..77768605 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -155,7 +155,7 @@ class port_address(design.design): # The polarity must be switched if we have a hierarchical wordline # to compensate for the local array inverters - b = factory.create(module_type="bitcell") + b = factory.create(module_type=OPTS.bitcell) if local_array_size > 0: self.rbl_driver = factory.create(module_type="inv_dec", diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 9848341e..8fb5a8fe 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -33,7 +33,7 @@ class port_data(design.design): self.num_spare_cols = 0 if not bit_offsets: - bitcell = factory.create(module_type="bitcell") + bitcell = factory.create(module_type=OPTS.bitcell) self.bit_offsets = [] for i in range(self.num_cols + self.num_spare_cols): self.bit_offsets.append(i * bitcell.width) @@ -191,7 +191,7 @@ class port_data(design.design): # and mirroring happens correctly # Used for names/dimensions only - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) if self.port == 0: # Append an offset on the left @@ -270,7 +270,7 @@ class port_data(design.design): # create arrays of bitline and bitline_bar names for read, # write, or all ports - self.bitcell = factory.create(module_type="bitcell") + self.bitcell = factory.create(module_type=OPTS.bitcell) self.bl_names = self.bitcell.get_all_bl_names() self.br_names = self.bitcell.get_all_br_names() self.wl_names = self.bitcell.get_all_wl_names() diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 5c354c97..cc6373db 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -281,7 +281,7 @@ class replica_bitcell_array(bitcell_base_array): self.supplies = ["vdd", "gnd"] # Used for names/dimensions only - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) # Main array self.bitcell_array_inst=self.add_inst(name="bitcell_array", diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 3788909c..ad6e63dc 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -88,7 +88,7 @@ class replica_column(bitcell_base_array): self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell) self.add_mod(self.edge_cell) # Used for pin names only - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) def create_instances(self): self.cell_inst = {} diff --git a/compiler/modules/row_cap_array.py b/compiler/modules/row_cap_array.py index f327aecf..1995b45c 100644 --- a/compiler/modules/row_cap_array.py +++ b/compiler/modules/row_cap_array.py @@ -43,7 +43,7 @@ class row_cap_array(bitcell_base_array): self.dummy_cell = factory.create(module_type="row_cap_{}".format(OPTS.bitcell)) self.add_mod(self.dummy_cell) - self.cell = factory.create(module_type="bitcell") + self.cell = factory.create(module_type=OPTS.bitcell) def create_instances(self): """ Create the module instances used in this design """ diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index f7f08bf2..ce4e6911 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -97,7 +97,7 @@ class sense_amp_array(design.design): # This is just used for measurements, # so don't add the module - self.bitcell = factory.create(module_type="bitcell") + self.bitcell = factory.create(module_type=OPTS.bitcell) def create_sense_amp_array(self): self.local_insts = [] diff --git a/compiler/modules/wordline_buffer_array.py b/compiler/modules/wordline_buffer_array.py index 90703bc1..d3132861 100644 --- a/compiler/modules/wordline_buffer_array.py +++ b/compiler/modules/wordline_buffer_array.py @@ -59,7 +59,7 @@ class wordline_buffer_array(design.design): self.add_pin("gnd", "GROUND") def add_modules(self): - b = factory.create(module_type="bitcell") + b = factory.create(module_type=OPTS.bitcell) self.wl_driver = factory.create(module_type="inv_dec", size=self.cols, diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 6806f034..aa0a4e29 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -99,7 +99,7 @@ class write_driver_array(design.design): # This is just used for measurements, # so don't add the module - self.bitcell = factory.create(module_type="bitcell") + self.bitcell = factory.create(module_type=OPTS.bitcell) def create_write_array(self): self.driver_insts = [] diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index db8c4e1d..ae5d8550 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -81,7 +81,7 @@ class write_mask_and_array(design.design): # This ensures the write mask AND array will be directly under the corresponding write driver enable wire. # This is just used for measurements, so don't add the module - self.bitcell = factory.create(module_type="bitcell") + self.bitcell = factory.create(module_type=OPTS.bitcell) self.driver = factory.create(module_type="write_driver") if self.bitcell.width > self.driver.width: self.driver_spacing = self.bitcell.width