Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.

2026-09-01 10:39:35 +02:00 · 2018-11-13 22:24:18 -08:00
parent 6f6d45f025
commit 8b6a28b6fd
5 changed files with 116 additions and 119 deletions
@@ -31,6 +31,7 @@ class control_logic(design.design):
        
        #This is needed to resize the delay chain. Likely to be changed at some point.
        self.sram=sram
+        #self.sram=None #disable re-sizing for debugging
        self.wl_timing_tolerance = 1 #Determines how much larger the sen delay should be. Accounts for possible error in model.
        self.parasitic_inv_delay = 0 #Keeping 0 for now until further testing.