luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix polarity problem.

Browse Source
This commit is contained in:
Matt Guthaus
2019-01-23 13:08:43 -08:00
parent d64d262d78
commit 8a85d3141a
1 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/control_logic.py
+3 -2
View File
@@ -87,7 +87,7 @@ class control_logic(design.design):
# Special gates: inverters for buffering
# clk_buf drives a flop for every address and control bit
clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2) + self.num_control_signals
#clock_fanout = max(1,int(self.num_rows/4))
self.clkbuf = factory.create(module_type="pdriver",
fanout=clock_fanout,
height=dff_height)
@@ -102,7 +102,7 @@ class control_logic(design.design):
# w_en drives every write driver
self.w_en_driver = factory.create(module_type="pdriver",
fanout=self.word_size,
fanout=self.word_size+8,
height=dff_height)
self.add_mod(self.w_en_driver)
@@ -120,6 +120,7 @@ class control_logic(design.design):
# p_en_bar drives every column in the bicell array
self.p_en_bar_driver = factory.create(module_type="pdriver",
neg_polarity=True,
fanout=self.num_cols,
height=dff_height)
self.add_mod(self.p_en_bar_driver)