diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index e2f93b16..9321ccd0 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -87,7 +87,7 @@ class control_logic(design.design):
         # Special gates: inverters for buffering
         # clk_buf drives a flop for every address and control bit
         clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2) + self.num_control_signals
-
+        #clock_fanout = max(1,int(self.num_rows/4))
         self.clkbuf = factory.create(module_type="pdriver",
                                      fanout=clock_fanout,
                                      height=dff_height)
@@ -102,7 +102,7 @@ class control_logic(design.design):
 
         # w_en drives every write driver
         self.w_en_driver = factory.create(module_type="pdriver",
-                                          fanout=self.word_size,
+                                          fanout=self.word_size+8,
                                           height=dff_height)
         self.add_mod(self.w_en_driver)
 
@@ -120,6 +120,7 @@ class control_logic(design.design):
 
         # p_en_bar drives every column in the bicell array
         self.p_en_bar_driver = factory.create(module_type="pdriver",
+                                              neg_polarity=True,
                                               fanout=self.num_cols,
                                               height=dff_height)
         self.add_mod(self.p_en_bar_driver)