luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity

proper tiling

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2023-07-26 18:05:36 -07:00
parent 4baec81f82
commit 8a4b34dee1
3 changed files with 20 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bitcell_array.py
+2 -2
View File
@@ -76,8 +76,8 @@ class bitcell_array(bitcell_base_array):
core_block = [[0 for x in range(2)] for y in range(2)]
core_block[0][0] = geometry.instance("core_0_0", mod=self.cell)
core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, mirror="MX")
core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, mirror="MY")
core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, mirror="MY")
core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, mirror="MX")
core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, mirror="XY")
num_core_x = self.row_size/len(core_block[0])
num_core_y = self.column_size/len(core_block)