From 88f43cc75421f0c48b3886b99f32437111878bb3 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 24 Oct 2018 16:41:33 -0700 Subject: [PATCH] Add the minimum pin enclosure that has DRC correct pin connections. --- compiler/router/router.py | 4 +--- compiler/router/supply_router.py | 2 -- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/compiler/router/router.py b/compiler/router/router.py index f14cd9f3..a3878b5e 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -624,8 +624,6 @@ class router: # Blockages will be a super-set of pins since it uses the inflated pin shape. blockage_in_tracks = self.convert_blockage(pin) blockage_set.update(blockage_in_tracks) - debug.info(2," .pins {}".format(pin_set)) - debug.info(2," .blocks {}".format(blockage_set)) # If we have a blockage, we must remove the grids # Remember, this excludes the pin blockages already @@ -839,7 +837,7 @@ class router: - self.write_debug_gds("pin_debug.gds", True) + #self.write_debug_gds("pin_debug.gds", True) def compute_enclosure(self, pin, enclosure): """ diff --git a/compiler/router/supply_router.py b/compiler/router/supply_router.py index c1282c04..597b6b1d 100644 --- a/compiler/router/supply_router.py +++ b/compiler/router/supply_router.py @@ -98,8 +98,6 @@ class supply_router(router): return True - - def route_simple_overlaps(self, pin_name):