mirror of https://github.com/VLSIDA/OpenRAM.git
Always use min area power/IO pins
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parent
3ef56a29ea
commit
88f2198524
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@ -56,8 +56,6 @@ class layout():
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self.visited = []
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self.visited = []
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# Flag for library cells
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# Flag for library cells
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self.is_library_cell = False
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self.is_library_cell = False
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# Flag for top level (used for min area metal pins etc.)
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self.is_top_level = False
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self.gds_read()
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self.gds_read()
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@ -1222,7 +1220,7 @@ class layout():
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pin.height())
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pin.height())
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elif add_vias:
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elif add_vias:
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self.add_power_pin(pin)
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self.copy_power_pin(pin)
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def add_io_pin(self, instance, pin_name, new_name, start_layer=None):
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def add_io_pin(self, instance, pin_name, new_name, start_layer=None):
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"""
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"""
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@ -1239,7 +1237,7 @@ class layout():
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def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
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def add_power_pin(self, name, loc, directions=None, start_layer="m1"):
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# Hack for min area
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# Hack for min area
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if OPTS.tech_name == "sky130" and self.is_top_level:
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if OPTS.tech_name == "sky130":
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min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
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min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
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width = round_to_grid(sqrt(min_area))
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width = round_to_grid(sqrt(min_area))
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height = round_to_grid(min_area / width)
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height = round_to_grid(min_area / width)
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@ -1280,7 +1278,7 @@ class layout():
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loc = pin.center()
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loc = pin.center()
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# Hack for min area
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# Hack for min area
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if OPTS.tech_name == "sky130" and self.is_top_level:
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if OPTS.tech_name == "sky130":
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min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
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min_area = drc["minarea_{}".format(self.pwr_grid_layer)]
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width = round_to_grid(sqrt(min_area))
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width = round_to_grid(sqrt(min_area))
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height = round_to_grid(min_area / width)
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height = round_to_grid(min_area / width)
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