diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py
index 2084c4ab..41b2ab83 100755
--- a/compiler/tests/04_pbitcell_test.py
+++ b/compiler/tests/04_pbitcell_test.py
@@ -13,9 +13,7 @@ import debug
 
 OPTS = globals.OPTS
 
-#@unittest.skip("SKIPPING 04_pbitcell_test")
-
-
+@unittest.skip("SKIPPING 04_pbitcell_test")
 class pbitcell_test(openram_test):
 
     def runTest(self):
diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py
index e8c16607..92e58673 100755
--- a/compiler/tests/05_pbitcell_array_test.py
+++ b/compiler/tests/05_pbitcell_array_test.py
@@ -11,7 +11,7 @@ import globals
 from globals import OPTS
 import debug
 
-#@unittest.skip("SKIPPING 05_pbitcell_array_test")
+@unittest.skip("SKIPPING 05_pbitcell_array_test")
 class pbitcell_array_test(openram_test):
 
     def runTest(self):
diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py
index e7ce8460..fad2b100 100755
--- a/compiler/tests/19_psingle_bank_test.py
+++ b/compiler/tests/19_psingle_bank_test.py
@@ -11,8 +11,8 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("Multiported Bank not working yet")
-class single_bank_test(openram_test):
+@unittest.skip("SKIPPING 19_psingle_bank_test")
+class psingle_bank_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))