Fix bitcell and pbitcell with different cell names

compiler/bitcells/bitcell_1w_1r.py

@@ -31,10 +31,10 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
                  "INPUT", "INPUT", "POWER", "GROUND"]
     storage_nets = ['Q', 'Q_bar']
 
-    def __init__(self, name, cell_name):
+    def __init__(self, name, cell_name=None):
         if not cell_name:
             cell_name = OPTS.bitcell_name
-        super().__init__(self, name, cell_name)
+        super().__init__(name, cell_name)
         debug.info(2, "Create bitcell with 1W and 1R Port")
 
         self.nets_match = self.do_nets_exist(self.storage_nets)

compiler/bitcells/dummy_pbitcell.py

@@ -17,13 +17,15 @@ class dummy_pbitcell(design.design):
     Creates a replica bitcell using pbitcell
     """
 
-    def __init__(self, name):
+    def __init__(self, name, cell_name=None):
+        if not cell_name:
+            cell_name = name
         self.num_rw_ports = OPTS.num_rw_ports
         self.num_w_ports = OPTS.num_w_ports
         self.num_r_ports = OPTS.num_r_ports
         self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
 
-        design.design.__init__(self, name, name)
+        design.design.__init__(self, name, cell_name)
         debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
                                                                                                                     self.num_w_ports,
                                                                                                                     self.num_r_ports))

compiler/bitcells/pbitcell.py

@@ -21,7 +21,9 @@ class pbitcell(bitcell_base.bitcell_base):
     with a variable number of read/write, write, and read ports
     """
 
-    def __init__(self, name, replica_bitcell=False, dummy_bitcell=False):
+    def __init__(self, name, cell_name=None, replica_bitcell=False, dummy_bitcell=False):
+        if not cell_name:
+            cell_name = name
         self.num_rw_ports = OPTS.num_rw_ports
         self.num_w_ports = OPTS.num_w_ports
         self.num_r_ports = OPTS.num_r_ports
@@ -30,7 +32,7 @@ class pbitcell(bitcell_base.bitcell_base):
         self.replica_bitcell = replica_bitcell
         self.dummy_bitcell = dummy_bitcell
 
-        bitcell_base.bitcell_base.__init__(self, name, name, hard_cell=False)
+        bitcell_base.bitcell_base.__init__(self, name, cell_name, hard_cell=False)
         fmt_str = "{0} rw ports, {1} w ports and {2} r ports"
         info_string = fmt_str.format(self.num_rw_ports,
                                      self.num_w_ports,

compiler/bitcells/replica_pbitcell.py

@@ -17,13 +17,15 @@ class replica_pbitcell(design.design):
     Creates a replica bitcell using pbitcell
     """
 
-    def __init__(self, name):
+    def __init__(self, name, cell_name=None):
+        if not cell_name:
+            cell_name = name
         self.num_rw_ports = OPTS.num_rw_ports
         self.num_w_ports = OPTS.num_w_ports
         self.num_r_ports = OPTS.num_r_ports
         self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
 
-        design.design.__init__(self, name, name)
+        design.design.__init__(self, name, cell_name)
         debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
                                                                                                                       self.num_w_ports,
                                                                                                                       self.num_r_ports))

compiler/globals.py

@@ -232,6 +232,13 @@ def setup_bitcell():
 
         OPTS.replica_bitcell = "replica_" + OPTS.bitcell
         OPTS.replica_bitcell_name = "replica_" + OPTS.bitcell_name
+    elif (OPTS.bitcell == "pbitcell"):
+        OPTS.bitcell = "pbitcell"
+        OPTS.bitcell_name = "pbitcell"
+        OPTS.dummy_bitcell = "dummy_pbitcell"
+        OPTS.dummy_bitcell_name = "dummy_pbitcell"
+        OPTS.replica_bitcell = "replica_pbitcell"
+        OPTS.replica_bitcell_name = "replica_pbitcell"
                 
     # See if bitcell exists
     try:
@@ -241,6 +248,11 @@ def setup_bitcell():
         # or its custom replica  bitcell
         # Use the pbitcell (and give a warning if not in unit test mode)
         OPTS.bitcell = "pbitcell"
+        OPTS.bitcell_name = "pbitcell"
+        OPTS.dummy_bitcell = "dummy_pbitcell"
+        OPTS.dummy_bitcell_name = "dummy_pbitcell"
+        OPTS.replica_bitcell = "replica_pbitcell"
+        OPTS.replica_bitcell_name = "replica_pbitcell"
         if not OPTS.is_unit_test:
             debug.warning("Using the parameterized bitcell which may have suboptimal density.")
     debug.info(1, "Using bitcell: {}".format(OPTS.bitcell))

compiler/tests/18_port_data_spare_cols_test.py

@@ -6,13 +6,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class port_data_spare_cols_test(openram_test):
 
     def runTest(self):
@@ -58,10 +59,10 @@ class port_data_spare_cols_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
 
-        OPTS.bitcell = "bitcell_1w_1r"
         OPTS.num_rw_ports = 0
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
+        globals.setup_bitcell()
         
         c.num_words=16
         c.words_per_row=1

compiler/tests/19_psingle_bank_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 19_psingle_bank_test")
+
 class psingle_bank_test(openram_test):
 
     def runTest(self):
@@ -30,6 +30,7 @@ class psingle_bank_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_1w_1r_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class single_bank_1w_1r_test(openram_test):
 
     def runTest(self):

compiler/tests/19_single_bank_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class single_bank_test(openram_test):
 
     def runTest(self):

compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
+    
 class psram_1bank_2mux_1rw_1w_test(openram_test):
 
     def runTest(self):

compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py

@@ -9,7 +9,6 @@
 import unittest
 from testutils import *
 import sys, os
-
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
@@ -26,11 +25,10 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
         from sram_config import sram_config
 
         OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell = "replica_pbitcell"
-        OPTS.dummy_bitcell = "dummy_pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=8,
                         write_size=4,

compiler/tests/20_psram_1bank_2mux_1w_1r_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
+
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):

compiler/tests/20_psram_1bank_2mux_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error")
+
 class psram_1bank_2mux_test(openram_test):
 
     def runTest(self):

compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class psram_1bank_4mux_1rw_1r_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class sram_1bank_2mux_1rw_1r_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_sram_1bank_2mux_1w_1r_spare_cols_test, odd supply routing error")
+
 class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_2mux_1w_1r_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
+
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_2mux_global_test.py

@@ -16,7 +16,6 @@ from sram_factory import factory
 import debug
 
 
-#@unittest.skip("SKIPPING 20_sram_1bank_4mux_test")
 class sram_1bank_2mux_global_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_2mux_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_sram_1bank_2mux_test")
+
 class sram_1bank_2mux_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py

@@ -9,14 +9,13 @@
 import unittest
 from testutils import *
 import sys, os
-
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_spare_cols_test")
+
 class sram_1bank_2mux_wmask_spare_cols_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_2mux_wmask_test.py

@@ -9,7 +9,6 @@
 import unittest
 from testutils import *
 import sys, os
-
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
@@ -17,7 +16,6 @@ from sram_factory import factory
 import debug
 
 
-# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_test")
 class sram_1bank_2mux_wmask_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_32b_1024_wmask_test.py

@@ -9,7 +9,6 @@
 import unittest
 from testutils import *
 import sys, os
-
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS

compiler/tests/20_sram_1bank_4mux_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_sram_1bank_4mux_test")
+
 class sram_1bank_4mux_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class sram_1bank_8mux_1rw_1r_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_8mux_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_sram_1bank_8mux_test")
+
 class sram_1bank_8mux_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class sram_1bank_nomux_1rw_1r_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_nomux_spare_cols_test.py

@@ -9,7 +9,6 @@
 import unittest
 from testutils import *
 import sys, os
-
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
@@ -17,7 +16,6 @@ from sram_factory import factory
 import debug
 
 
-# @unittest.skip("SKIPPING 20_sram_1bank_nomux_spare_cols_test")
 class sram_1bank_nomux_spare_cols_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_nomux_test.py

@@ -8,14 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 20_sram_1bank_nomux_test")
+
 class sram_1bank_nomux_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py

@@ -9,7 +9,6 @@
 import unittest
 from testutils import *
 import sys, os
-
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS

compiler/tests/20_sram_1bank_nomux_wmask_test.py

@@ -9,7 +9,6 @@
 import unittest
 from testutils import *
 import sys, os
-
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
@@ -17,7 +16,6 @@ from sram_factory import factory
 import debug
 
 
-# @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_test")
 class sram_1bank_nomux_wmask_test(openram_test):
 
     def runTest(self):

compiler/tests/20_sram_2bank_test.py

@@ -8,13 +8,14 @@
 #
 import unittest
 from testutils import *
-import sys,os
+import sys, os
 sys.path.append(os.getenv("OPENRAM_HOME"))
 import globals
 from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 @unittest.skip("Multibank is not working yet.")
 class sram_2bank_test(openram_test):
 

technology/scn4m_subm/tech/setup.tcl

@@ -9,9 +9,13 @@ flatten class {-circuit1 dummy_cell_1w_1r}
 flatten class {-circuit1 dummy_pbitcell}
 flatten class {-circuit1 dummy_pbitcell_0}
 flatten class {-circuit1 dummy_pbitcell_1}
+flatten class {-circuit1 dummy_pbitcell_2}
+flatten class {-circuit1 dummy_pbitcell_3}
 flatten class {-circuit1 pbitcell}
 flatten class {-circuit1 pbitcell_0}
 flatten class {-circuit1 pbitcell_1}
+flatten class {-circuit1 pbitcell_2}
+flatten class {-circuit1 pbitcell_3}
 property {-circuit1 nfet} remove as ad ps pd
 property {-circuit1 pfet} remove as ad ps pd
 property {-circuit2 n} remove as ad ps pd