From 87419bd640505ddf496fed07a968346cd5b44088 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 3 Nov 2020 11:30:40 -0800 Subject: [PATCH] Fix bitcell and pbitcell with different cell names --- compiler/bitcells/bitcell_1w_1r.py | 4 ++-- compiler/bitcells/dummy_pbitcell.py | 6 ++++-- compiler/bitcells/pbitcell.py | 6 ++++-- compiler/bitcells/replica_pbitcell.py | 6 ++++-- compiler/globals.py | 14 +++++++++++++- compiler/tests/18_port_data_spare_cols_test.py | 7 ++++--- compiler/tests/19_psingle_bank_test.py | 7 ++++--- compiler/tests/19_single_bank_1w_1r_test.py | 3 ++- compiler/tests/19_single_bank_test.py | 3 ++- compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py | 4 ++-- .../tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py | 6 ++---- compiler/tests/20_psram_1bank_2mux_1w_1r_test.py | 4 ++-- compiler/tests/20_psram_1bank_2mux_test.py | 4 ++-- compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py | 3 ++- .../20_sram_1bank_2mux_1rw_1r_spare_cols_test.py | 3 ++- compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py | 3 ++- .../20_sram_1bank_2mux_1w_1r_spare_cols_test.py | 4 ++-- compiler/tests/20_sram_1bank_2mux_1w_1r_test.py | 4 ++-- compiler/tests/20_sram_1bank_2mux_global_test.py | 1 - compiler/tests/20_sram_1bank_2mux_test.py | 4 ++-- .../20_sram_1bank_2mux_wmask_spare_cols_test.py | 3 +-- compiler/tests/20_sram_1bank_2mux_wmask_test.py | 2 -- .../tests/20_sram_1bank_32b_1024_wmask_test.py | 1 - compiler/tests/20_sram_1bank_4mux_test.py | 4 ++-- compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py | 3 ++- compiler/tests/20_sram_1bank_8mux_test.py | 4 ++-- .../20_sram_1bank_nomux_1rw_1r_spare_cols_test.py | 3 ++- compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py | 3 ++- .../tests/20_sram_1bank_nomux_spare_cols_test.py | 2 -- compiler/tests/20_sram_1bank_nomux_test.py | 4 ++-- .../20_sram_1bank_nomux_wmask_sparecols_test.py | 1 - compiler/tests/20_sram_1bank_nomux_wmask_test.py | 2 -- compiler/tests/20_sram_2bank_test.py | 3 ++- technology/scn4m_subm/tech/setup.tcl | 4 ++++ 34 files changed, 78 insertions(+), 57 deletions(-) diff --git a/compiler/bitcells/bitcell_1w_1r.py b/compiler/bitcells/bitcell_1w_1r.py index 06a862e4..02b6e768 100644 --- a/compiler/bitcells/bitcell_1w_1r.py +++ b/compiler/bitcells/bitcell_1w_1r.py @@ -31,10 +31,10 @@ class bitcell_1w_1r(bitcell_base.bitcell_base): "INPUT", "INPUT", "POWER", "GROUND"] storage_nets = ['Q', 'Q_bar'] - def __init__(self, name, cell_name): + def __init__(self, name, cell_name=None): if not cell_name: cell_name = OPTS.bitcell_name - super().__init__(self, name, cell_name) + super().__init__(name, cell_name) debug.info(2, "Create bitcell with 1W and 1R Port") self.nets_match = self.do_nets_exist(self.storage_nets) diff --git a/compiler/bitcells/dummy_pbitcell.py b/compiler/bitcells/dummy_pbitcell.py index 9b6078c7..4ece44c4 100644 --- a/compiler/bitcells/dummy_pbitcell.py +++ b/compiler/bitcells/dummy_pbitcell.py @@ -17,13 +17,15 @@ class dummy_pbitcell(design.design): Creates a replica bitcell using pbitcell """ - def __init__(self, name): + def __init__(self, name, cell_name=None): + if not cell_name: + cell_name = name self.num_rw_ports = OPTS.num_rw_ports self.num_w_ports = OPTS.num_w_ports self.num_r_ports = OPTS.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports - design.design.__init__(self, name, name) + design.design.__init__(self, name, cell_name) debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, self.num_w_ports, self.num_r_ports)) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index c836e083..e2cdd032 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -21,7 +21,9 @@ class pbitcell(bitcell_base.bitcell_base): with a variable number of read/write, write, and read ports """ - def __init__(self, name, replica_bitcell=False, dummy_bitcell=False): + def __init__(self, name, cell_name=None, replica_bitcell=False, dummy_bitcell=False): + if not cell_name: + cell_name = name self.num_rw_ports = OPTS.num_rw_ports self.num_w_ports = OPTS.num_w_ports self.num_r_ports = OPTS.num_r_ports @@ -30,7 +32,7 @@ class pbitcell(bitcell_base.bitcell_base): self.replica_bitcell = replica_bitcell self.dummy_bitcell = dummy_bitcell - bitcell_base.bitcell_base.__init__(self, name, name, hard_cell=False) + bitcell_base.bitcell_base.__init__(self, name, cell_name, hard_cell=False) fmt_str = "{0} rw ports, {1} w ports and {2} r ports" info_string = fmt_str.format(self.num_rw_ports, self.num_w_ports, diff --git a/compiler/bitcells/replica_pbitcell.py b/compiler/bitcells/replica_pbitcell.py index 04b072ba..710cf81d 100644 --- a/compiler/bitcells/replica_pbitcell.py +++ b/compiler/bitcells/replica_pbitcell.py @@ -17,13 +17,15 @@ class replica_pbitcell(design.design): Creates a replica bitcell using pbitcell """ - def __init__(self, name): + def __init__(self, name, cell_name=None): + if not cell_name: + cell_name = name self.num_rw_ports = OPTS.num_rw_ports self.num_w_ports = OPTS.num_w_ports self.num_r_ports = OPTS.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports - design.design.__init__(self, name, name) + design.design.__init__(self, name, cell_name) debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, self.num_w_ports, self.num_r_ports)) diff --git a/compiler/globals.py b/compiler/globals.py index 458ec04e..9e05efcb 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -232,7 +232,14 @@ def setup_bitcell(): OPTS.replica_bitcell = "replica_" + OPTS.bitcell OPTS.replica_bitcell_name = "replica_" + OPTS.bitcell_name - + elif (OPTS.bitcell == "pbitcell"): + OPTS.bitcell = "pbitcell" + OPTS.bitcell_name = "pbitcell" + OPTS.dummy_bitcell = "dummy_pbitcell" + OPTS.dummy_bitcell_name = "dummy_pbitcell" + OPTS.replica_bitcell = "replica_pbitcell" + OPTS.replica_bitcell_name = "replica_pbitcell" + # See if bitcell exists try: __import__(OPTS.bitcell) @@ -241,6 +248,11 @@ def setup_bitcell(): # or its custom replica bitcell # Use the pbitcell (and give a warning if not in unit test mode) OPTS.bitcell = "pbitcell" + OPTS.bitcell_name = "pbitcell" + OPTS.dummy_bitcell = "dummy_pbitcell" + OPTS.dummy_bitcell_name = "dummy_pbitcell" + OPTS.replica_bitcell = "replica_pbitcell" + OPTS.replica_bitcell_name = "replica_pbitcell" if not OPTS.is_unit_test: debug.warning("Using the parameterized bitcell which may have suboptimal density.") debug.info(1, "Using bitcell: {}".format(OPTS.bitcell)) diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index 953199d6..0ec87d5f 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -6,13 +6,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class port_data_spare_cols_test(openram_test): def runTest(self): @@ -58,11 +59,11 @@ class port_data_spare_cols_test(openram_test): a = factory.create("port_data", sram_config=c, port=0) self.local_check(a) - OPTS.bitcell = "bitcell_1w_1r" OPTS.num_rw_ports = 0 OPTS.num_r_ports = 1 OPTS.num_w_ports = 1 - + globals.setup_bitcell() + c.num_words=16 c.words_per_row=1 factory.reset() diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index d666155d..5c6bc418 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 19_psingle_bank_test") + class psingle_bank_test(openram_test): def runTest(self): @@ -30,7 +30,8 @@ class psingle_bank_test(openram_test): OPTS.num_rw_ports = 1 OPTS.num_w_ports = 0 OPTS.num_r_ports = 0 - + globals.setup_bitcell() + c = sram_config(word_size=4, num_words=16) diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py index 02846cfd..1eef7c93 100755 --- a/compiler/tests/19_single_bank_1w_1r_test.py +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class single_bank_1w_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index e7d4c328..db6776e3 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class single_bank_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index 5d99ea06..1ba44598 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") + class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py index 0d236bc2..23b2d490 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -26,12 +25,11 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test): from sram_config import sram_config OPTS.bitcell = "pbitcell" - OPTS.replica_bitcell = "replica_pbitcell" - OPTS.dummy_bitcell = "dummy_pbitcell" OPTS.num_rw_ports = 1 OPTS.num_w_ports = 1 OPTS.num_r_ports = 0 - + globals.setup_bitcell() + c = sram_config(word_size=8, write_size=4, num_words=32, diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 49b84cbe..1e82ea4f 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") + class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 421b08be..7ce30ecf 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error") + class psram_1bank_2mux_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 519517e7..45de93e5 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py index fe8d42ab..8887ca5b 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 9d2dc853..bac2fd5f 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py index 40c208ee..83c8cc75 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_sram_1bank_2mux_1w_1r_spare_cols_test, odd supply routing error") + class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 754ceed3..53dc4a8d 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") + class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_2mux_global_test.py b/compiler/tests/20_sram_1bank_2mux_global_test.py index cb8571da..93caeb86 100755 --- a/compiler/tests/20_sram_1bank_2mux_global_test.py +++ b/compiler/tests/20_sram_1bank_2mux_global_test.py @@ -16,7 +16,6 @@ from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_sram_1bank_4mux_test") class sram_1bank_2mux_global_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 536ba683..2ce4704b 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_sram_1bank_2mux_test") + class sram_1bank_2mux_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py index 0488b93e..6a513288 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py @@ -9,14 +9,13 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_spare_cols_test") + class sram_1bank_2mux_wmask_spare_cols_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py index 50bd41dc..fc7f2a8d 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -17,7 +16,6 @@ from sram_factory import factory import debug -# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_test") class sram_1bank_2mux_wmask_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py index 05cb7c0d..7717242f 100755 --- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py +++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index e27fca71..f4791105 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_sram_1bank_4mux_test") + class sram_1bank_4mux_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index 07be8e37..167602d7 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index 501fbe3d..5d65e02a 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_sram_1bank_8mux_test") + class sram_1bank_8mux_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py index e68f2401..4175f01d 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index 95544297..81b13c0e 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py index 135518e3..410fedea 100755 --- a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -17,7 +16,6 @@ from sram_factory import factory import debug -# @unittest.skip("SKIPPING 20_sram_1bank_nomux_spare_cols_test") class sram_1bank_nomux_spare_cols_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 44d583b7..524172bd 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -8,14 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_sram_1bank_nomux_test") + class sram_1bank_nomux_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py index e22122bd..4d2e2c4a 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py index 24d7c97d..01282521 100755 --- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py +++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py @@ -9,7 +9,6 @@ import unittest from testutils import * import sys, os - sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -17,7 +16,6 @@ from sram_factory import factory import debug -# @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_test") class sram_1bank_nomux_wmask_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index 53f87eba..a6cb3e1a 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -8,13 +8,14 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug + @unittest.skip("Multibank is not working yet.") class sram_2bank_test(openram_test): diff --git a/technology/scn4m_subm/tech/setup.tcl b/technology/scn4m_subm/tech/setup.tcl index 40de5ac1..968c5c01 100644 --- a/technology/scn4m_subm/tech/setup.tcl +++ b/technology/scn4m_subm/tech/setup.tcl @@ -9,9 +9,13 @@ flatten class {-circuit1 dummy_cell_1w_1r} flatten class {-circuit1 dummy_pbitcell} flatten class {-circuit1 dummy_pbitcell_0} flatten class {-circuit1 dummy_pbitcell_1} +flatten class {-circuit1 dummy_pbitcell_2} +flatten class {-circuit1 dummy_pbitcell_3} flatten class {-circuit1 pbitcell} flatten class {-circuit1 pbitcell_0} flatten class {-circuit1 pbitcell_1} +flatten class {-circuit1 pbitcell_2} +flatten class {-circuit1 pbitcell_3} property {-circuit1 nfet} remove as ad ps pd property {-circuit1 pfet} remove as ad ps pd property {-circuit2 n} remove as ad ps pd