luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

complete log file generation

This commit is contained in:
Jesse Cirimelli-Low 2019-01-13 14:34:46 -08:00
parent e210ef2a41
commit 87380a4801
4 changed files with 70 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
compiler/debug.py
View File

@ -14,20 +14,51 @@ def check(check,str):
index) = inspect.getouterframes(inspect.currentframe())[1] index) = inspect.getouterframes(inspect.currentframe())[1]
if not check: if not check:
sys.stderr.write("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str)) sys.stderr.write("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
log("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
assert 0 assert 0
def error(str,return_value=0): def error(str,return_value=0):
(frame, filename, line_number, function_name, lines, (frame, filename, line_number, function_name, lines,
index) = inspect.getouterframes(inspect.currentframe())[1] index) = inspect.getouterframes(inspect.currentframe())[1]
sys.stderr.write("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str)) sys.stderr.write("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
log("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
assert return_value==0 assert return_value==0
def warning(str): def warning(str):
(frame, filename, line_number, function_name, lines, (frame, filename, line_number, function_name, lines,
index) = inspect.getouterframes(inspect.currentframe())[1] index) = inspect.getouterframes(inspect.currentframe())[1]
sys.stderr.write("WARNING: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str)) sys.stderr.write("WARNING: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
log("WARNING: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
def print_raw(str):
print(str)
log(str)
def log(str):
try:
if log.create_file:
compile_log = open(globals.OPTS.output_path + globals.OPTS.output_name + '.log',"w+")
log.create_file = 0
else:
compile_log = open(globals.OPTS.output_path + globals.OPTS.output_name + '.log',"a")
if len(log.setup_output) != 0:
for line in log.setup_output:
compile_log.write(line)
log.setup_output = []
compile_log.write(str + '\n')
except:
log.setup_out.append(str + "\n")
#use a static list of strings to store messages until the global paths are set up
log.setup_output = []
log.create_file = 1
def info(lev, str): def info(lev, str):
from globals import OPTS from globals import OPTS
if (OPTS.debug_level >= lev): if (OPTS.debug_level >= lev):

48
compiler/globals.py
View File

@ -71,26 +71,26 @@ def print_banner():
if OPTS.is_unit_test: if OPTS.is_unit_test:
return return
print("|==============================================================================|") debug.print_raw("|==============================================================================|")
name = "OpenRAM Compiler" name = "OpenRAM Compiler"
print("|=========" + name.center(60) + "=========|") debug.print_raw("|=========" + name.center(60) + "=========|")
print("|=========" + " ".center(60) + "=========|") debug.print_raw("|=========" + " ".center(60) + "=========|")
print("|=========" + "VLSI Design and Automation Lab".center(60) + "=========|") debug.print_raw("|=========" + "VLSI Design and Automation Lab".center(60) + "=========|")
print("|=========" + "Computer Science and Engineering Department".center(60) + "=========|") debug.print_raw("|=========" + "Computer Science and Engineering Department".center(60) + "=========|")
print("|=========" + "University of California Santa Cruz".center(60) + "=========|") debug.print_raw("|=========" + "University of California Santa Cruz".center(60) + "=========|")
print("|=========" + " ".center(60) + "=========|") debug.print_raw("|=========" + " ".center(60) + "=========|")
print("|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|") debug.print_raw("|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|")
print("|=========" + "Electrical and Computer Engineering Department".center(60) + "=========|") debug.print_raw("|=========" + "Electrical and Computer Engineering Department".center(60) + "=========|")
print("|=========" + "Oklahoma State University".center(60) + "=========|") debug.print_raw("|=========" + "Oklahoma State University".center(60) + "=========|")
print("|=========" + " ".center(60) + "=========|") debug.print_raw("|=========" + " ".center(60) + "=========|")
user_info = "Usage help: openram-user-group@ucsc.edu" user_info = "Usage help: openram-user-group@ucsc.edu"
print("|=========" + user_info.center(60) + "=========|") debug.print_raw("|=========" + user_info.center(60) + "=========|")
dev_info = "Development help: openram-dev-group@ucsc.edu" dev_info = "Development help: openram-dev-group@ucsc.edu"
print("|=========" + dev_info.center(60) + "=========|") debug.print_raw("|=========" + dev_info.center(60) + "=========|")
temp_info = "Temp dir: {}".format(OPTS.openram_temp) temp_info = "Temp dir: {}".format(OPTS.openram_temp)
print("|=========" + temp_info.center(60) + "=========|") debug.print_raw("|=========" + temp_info.center(60) + "=========|")
print("|=========" + "See LICENSE for license info".center(60) + "=========|") debug.print_raw("|=========" + "See LICENSE for license info".center(60) + "=========|")
print("|==============================================================================|") debug.print_raw("|==============================================================================|")
def check_versions(): def check_versions():
@ -397,7 +397,7 @@ def print_time(name, now_time, last_time=None, indentation=2):
time = str(round((now_time-last_time).total_seconds(),1)) + " seconds" time = str(round((now_time-last_time).total_seconds(),1)) + " seconds"
else: else:
time = now_time.strftime('%m/%d/%Y %H:%M:%S') time = now_time.strftime('%m/%d/%Y %H:%M:%S')
print("{0} {1}: {2}".format("*"*indentation,name,time)) debug.print_raw("{0} {1}: {2}".format("*"*indentation,name,time))
def report_status(): def report_status():
@ -413,20 +413,20 @@ def report_status():
if not OPTS.tech_name: if not OPTS.tech_name:
debug.error("Tech name must be specified in config file.") debug.error("Tech name must be specified in config file.")
print("Technology: {0}".format(OPTS.tech_name)) debug.print_raw("Technology: {0}".format(OPTS.tech_name))
print("Total size: {} bits".format(OPTS.word_size*OPTS.num_words*OPTS.num_banks)) debug.print_raw("Total size: {} bits".format(OPTS.word_size*OPTS.num_words*OPTS.num_banks))
print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size, debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
OPTS.num_words, OPTS.num_words,
OPTS.num_banks)) OPTS.num_banks))
print("RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format(OPTS.num_rw_ports, debug.print_raw("RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format(OPTS.num_rw_ports,
OPTS.num_r_ports, OPTS.num_r_ports,
OPTS.num_w_ports)) OPTS.num_w_ports))
if OPTS.netlist_only: if OPTS.netlist_only:
print("Netlist only mode (no physical design is being done).") debug.print_raw("Netlist only mode (no physical design is being done).")
if not OPTS.inline_lvsdrc: if not OPTS.inline_lvsdrc:
print("DRC/LVS/PEX is only run on the top-level design.") debug.print_raw("DRC/LVS/PEX is only run on the top-level design.")
if not OPTS.check_lvsdrc: if not OPTS.check_lvsdrc:
print("DRC/LVS/PEX is completely disabled.") debug.print_raw("DRC/LVS/PEX is completely disabled.")

9
compiler/openram.py
View File

@ -44,15 +44,16 @@ from sram_config import sram_config
# Configure the SRAM organization # Configure the SRAM organization
c = sram_config(word_size=OPTS.word_size, c = sram_config(word_size=OPTS.word_size,
num_words=OPTS.num_words) num_words=OPTS.num_words)
print("Words per row: {}".format(c.words_per_row)) debug.print_raw("Words per row: {}".format(c.words_per_row))
#from parser import * #from parser import *
output_extensions = ["sp","v","lib","py","html"] output_extensions = ["sp","v","lib","py","html","log"]
if not OPTS.netlist_only: if not OPTS.netlist_only:
output_extensions.extend(["gds","lef"]) output_extensions.extend(["gds","lef"])
output_files = ["{0}{1}.{2}".format(OPTS.output_path,OPTS.output_name,x) for x in output_extensions] output_files = ["{0}{1}.{2}".format(OPTS.output_path,OPTS.output_name,x) for x in output_extensions]
print("Output files are: ") debug.print_raw("Output files are: ")
print(*output_files,sep="\n") for path in output_files:
debug.print_raw(path)
from sram import sram from sram import sram

20
compiler/sram.py
View File

@ -65,21 +65,21 @@ class sram():
# Write the layout # Write the layout
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
gdsname = OPTS.output_path + self.s.name + ".gds" gdsname = OPTS.output_path + self.s.name + ".gds"
print("GDS: Writing to {0}".format(gdsname)) debug.print_raw("GDS: Writing to {0}".format(gdsname))
self.gds_write(gdsname) self.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time) print_time("GDS", datetime.datetime.now(), start_time)
# Create a LEF physical model # Create a LEF physical model
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
lefname = OPTS.output_path + self.s.name + ".lef" lefname = OPTS.output_path + self.s.name + ".lef"
print("LEF: Writing to {0}".format(lefname)) debug.print_raw("LEF: Writing to {0}".format(lefname))
self.lef_write(lefname) self.lef_write(lefname)
print_time("LEF", datetime.datetime.now(), start_time) print_time("LEF", datetime.datetime.now(), start_time)
# Save the spice file # Save the spice file
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
spname = OPTS.output_path + self.s.name + ".sp" spname = OPTS.output_path + self.s.name + ".sp"
print("SP: Writing to {0}".format(spname)) debug.print_raw("SP: Writing to {0}".format(spname))
self.sp_write(spname) self.sp_write(spname)
print_time("Spice writing", datetime.datetime.now(), start_time) print_time("Spice writing", datetime.datetime.now(), start_time)
@ -98,14 +98,14 @@ class sram():
# Characterize the design # Characterize the design
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
from characterizer import lib from characterizer import lib
print("LIB: Characterizing... ") debug.print_raw("LIB: Characterizing... ")
if OPTS.analytical_delay: if OPTS.analytical_delay:
print("Using analytical delay models (no characterization)") debug.print_raw("Using analytical delay models (no characterization)")
else: else:
if OPTS.spice_name!="": if OPTS.spice_name!="":
print("Performing simulation-based characterization with {}".format(OPTS.spice_name)) debug.print_raw("Performing simulation-based characterization with {}".format(OPTS.spice_name))
if OPTS.trim_netlist: if OPTS.trim_netlist:
print("Trimming netlist to speed up characterization.") debug.print_raw("Trimming netlist to speed up characterization.")
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
print_time("Characterization", datetime.datetime.now(), start_time) print_time("Characterization", datetime.datetime.now(), start_time)
@ -114,20 +114,20 @@ class sram():
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
from shutil import copyfile from shutil import copyfile
copyfile(OPTS.config_file + '.py', OPTS.output_path + OPTS.output_name + '.py') copyfile(OPTS.config_file + '.py', OPTS.output_path + OPTS.output_name + '.py')
print("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py')) debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
print_time("Config", datetime.datetime.now(), start_time) print_time("Config", datetime.datetime.now(), start_time)
# Write the datasheet # Write the datasheet
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
from datasheet_gen import datasheet_gen from datasheet_gen import datasheet_gen
dname = OPTS.output_path + self.s.name + ".html" dname = OPTS.output_path + self.s.name + ".html"
print("Datasheet: Writing to {0}".format(dname)) debug.print_raw("Datasheet: Writing to {0}".format(dname))
datasheet_gen.datasheet_write(self.s,dname) datasheet_gen.datasheet_write(self.s,dname)
print_time("Datasheet", datetime.datetime.now(), start_time) print_time("Datasheet", datetime.datetime.now(), start_time)
# Write a verilog model # Write a verilog model
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
vname = OPTS.output_path + self.s.name + ".v" vname = OPTS.output_path + self.s.name + ".v"
print("Verilog: Writing to {0}".format(vname)) debug.print_raw("Verilog: Writing to {0}".format(vname))
self.verilog_write(vname) self.verilog_write(vname)
print_time("Verilog", datetime.datetime.now(), start_time) print_time("Verilog", datetime.datetime.now(), start_time)