Small bug fixes related to new name mapping.

compiler/modules/col_cap_array.py

@@ -6,7 +6,6 @@
 from bitcell_base_array import bitcell_base_array
 from sram_factory import factory
 from globals import OPTS
-from tech import cell_properties
 
 
 class col_cap_array(bitcell_base_array):
@@ -65,16 +64,14 @@ class col_cap_array(bitcell_base_array):
         """
 
         if len(self.all_ports) == 1:
-            pin_name = cell_properties.bitcell.cell_6t.pin
-            bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
-                            "{0}_{1}".format(pin_name.br0, col),
+            bitcell_pins = ["bl0_{0}".format(col),
+                            "br0_{0}".format(col),
                             "vdd"]
         else:
-            pin_name = cell_properties.bitcell.cell_1rw1r.pin
-            bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
-                            "{0}_{1}".format(pin_name.br0, col),
-                            "{0}_{1}".format(pin_name.bl1, col),
-                            "{0}_{1}".format(pin_name.br1, col),
+            bitcell_pins = ["bl0_{0}".format(col),
+                            "br0_{0}".format(col),
+                            "bl1_{0}".format(col),
+                            "br1_{0}".format(col),
                             "vdd"]
 
         return bitcell_pins

compiler/modules/dff_buf.py

@@ -8,7 +8,6 @@
 import debug
 import design
 from tech import layer
-from tech import cell_properties as props
 from vector import vector
 from globals import OPTS
 from sram_factory import factory
@@ -72,9 +71,8 @@ class dff_buf(design.design):
         self.add_mod(self.inv2)
 
     def add_pins(self):
-        self.add_pin_names(props.dff_buf.port_map)
-        self.add_pin_list(props.dff_buf.port_names,
-                          props.dff_buf.port_types)
+        self.add_pin_list(["D", "Q", "Qb", "clk", "vdd", "gnd"],
+                          ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"])
 
     def create_instances(self):
         self.dff_inst=self.add_inst(name="dff_buf_dff",

compiler/modules/replica_column.py

@@ -5,7 +5,6 @@
 #
 import debug
 from bitcell_base_array import bitcell_base_array
-from tech import cell_properties as props
 from sram_factory import factory
 from vector import vector
 from globals import OPTS
@@ -31,8 +30,15 @@ class replica_column(bitcell_base_array):
         # left, right, regular rows plus top/bottom dummy cells
         self.total_size = self.left_rbl + rows + self.right_rbl
 
+        # Used for pin names and properties
+        self.cell = factory.create(module_type=OPTS.bitcell)
+        
         # For end caps
-        self.total_size += 2
+        try:
+            if not self.cell.end_caps:
+                self.total_size += 2
+        except AttributeError:
+            self.total_size += 2
 
         self.column_offset = column_offset
 
@@ -86,9 +92,6 @@ class replica_column(bitcell_base_array):
         self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell)
         self.add_mod(self.edge_cell)
 
-        # Used for pin names only
-        self.cell = factory.create(module_type=OPTS.bitcell)
-
     def create_instances(self):
         self.cell_inst = {}
 

compiler/modules/row_cap_array.py

@@ -6,7 +6,6 @@
 from bitcell_base_array import bitcell_base_array
 from sram_factory import factory
 from globals import OPTS
-from tech import cell_properties
 
 
 class row_cap_array(bitcell_base_array):
@@ -61,9 +60,8 @@ class row_cap_array(bitcell_base_array):
         indexed by column and row, for instance use in bitcell_array
         """
 
-        pin_name = cell_properties.bitcell.cell_1rw1r.pin
-        bitcell_pins = ["{0}_{1}".format(pin_name.wl0, row),
-                        "{0}_{1}".format(pin_name.wl1, row),
+        bitcell_pins = ["wl0_{0}".format(row),
+                        "wl1_{0}".format(row),
                         "gnd"]
 
         return bitcell_pins