luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Modify LEF output to have all capital LAYER. Remove extra space before new lines.

This commit is contained in:
Matt Guthaus 2017-08-15 08:21:54 -07:00
parent 550eadfa82
commit 857b997367
3 changed files with 191 additions and 191 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
compiler/lef.py
View File

@ -45,11 +45,11 @@ class lef:
for pin in input_pin_name: for pin in input_pin_name:
self.writePin(pin,4) self.writePin(pin,4)
self.lef.write(" OBS \n") self.lef.write(" OBS\n")
for lay in self.layer: for lay in self.layer:
self.lef.write(" Layer {0} ; \n".format(lay)) self.lef.write(" LAYER {0} ;\n".format(lay))
self.writeObstruct(self.sr.name, lay, mirr = 1, angle = math.radians(float(0)), xyShift = (0, 0)) self.writeObstruct(self.sr.name, lay, mirr = 1, angle = math.radians(float(0)), xyShift = (0, 0))
self.lef.write(" END \n") self.lef.write(" END\n")
self.writeLefFooter() self.writeLefFooter()
@ -160,8 +160,8 @@ class lef:
self.lef.write(" SYMMETRY X Y R90 ;\n") self.lef.write(" SYMMETRY X Y R90 ;\n")
def writeLefFooter(self): def writeLefFooter(self):
self.lef.write("END {0} \n".format(self.sr.name)) self.lef.write("END {0}\n".format(self.sr.name))
self.lef.write("END LIBRARY \n") self.lef.write("END LIBRARY\n")
def powerPinName(self): def powerPinName(self):
return ["vdd"] return ["vdd"]
@ -187,35 +187,35 @@ class lef:
return inout_pin_name return inout_pin_name
def writePin(self, pinName, typ): def writePin(self, pinName, typ):
self.lef.write(" PIN {0} \n".format(pinName)) self.lef.write(" PIN {0}\n".format(pinName))
if typ == 1: if typ == 1:
self.lef.write(" DIRECTION INOUT ; \n") self.lef.write(" DIRECTION INOUT ;\n")
self.lef.write(" USE POWER ; \n") self.lef.write(" USE POWER ;\n")
self.lef.write(" SHAPE ABUTMENT ; \n") self.lef.write(" SHAPE ABUTMENT ;\n")
self.lef.write(" PORT \n") self.lef.write(" PORT\n")
elif typ == 2: elif typ == 2:
self.lef.write(" DIRECTION INOUT ; \n") self.lef.write(" DIRECTION INOUT ;\n")
self.lef.write(" USE GROUND ; \n") self.lef.write(" USE GROUND ;\n")
self.lef.write(" SHAPE ABUTMENT ; \n") self.lef.write(" SHAPE ABUTMENT ;\n")
self.lef.write(" PORT \n") self.lef.write(" PORT\n")
elif typ == 3: elif typ == 3:
self.lef.write(" DIRECTION INOUT ; \n") self.lef.write(" DIRECTION INOUT ;\n")
self.lef.write(" PORT \n") self.lef.write(" PORT\n")
elif typ == 4: elif typ == 4:
self.lef.write(" DIRECTION INPUT ; \n") self.lef.write(" DIRECTION INPUT ;\n")
self.lef.write(" PORT \n") self.lef.write(" PORT\n")
else: else:
debug.error("Invalid pin type on pin {0}".format(pinName)) debug.error("Invalid pin type on pin {0}".format(pinName))
pin_layer_coord = self.pinLayerCoord(self.sr.name, pinName) pin_layer_coord = self.pinLayerCoord(self.sr.name, pinName)
for pinLayer in pin_layer_coord: for pinLayer in pin_layer_coord:
lay = [key for key, value in tech.layer.iteritems() if value == pinLayer][0] lay = [key for key, value in tech.layer.iteritems() if value == pinLayer][0]
self.lef.write(" Layer {0} ; \n".format(lay)) self.lef.write(" LAYER {0} ;\n".format(lay))
for pinCoord in pin_layer_coord[pinLayer]: for pinCoord in pin_layer_coord[pinLayer]:
self.writePinCoord(self.sr.name, pinName, pinLayer, pinCoord, self.writePinCoord(self.sr.name, pinName, pinLayer, pinCoord,
mirr = 1,angle = math.radians(float(0)), xyShift = (0, 0)) mirr = 1,angle = math.radians(float(0)), xyShift = (0, 0))
self.lef.write(" END \n") self.lef.write(" END\n")
self.lef.write(" END {0} \n".format(pinName)) self.lef.write(" END {0}\n".format(pinName))
def lowestLeftCorner(self, sr, mirr = 1, angle = math.radians(float(0)), xyShift = (0, 0), listMinX = [], listMinY = [], listMaxX = [], listMaxY =[]): def lowestLeftCorner(self, sr, mirr = 1, angle = math.radians(float(0)), xyShift = (0, 0), listMinX = [], listMinY = [], listMaxX = [], listMaxY =[]):
"""Recursive find a lowest left conner on each Structure in GDS file""" """Recursive find a lowest left conner on each Structure in GDS file"""

34
compiler/tests/golden/sram_2_16_1_freepdk45.lef
View File

@ -9,7 +9,7 @@ MACRO sram_2_16_1_freepdk45
USE POWER ; USE POWER ;
SHAPE ABUTMENT ; SHAPE ABUTMENT ;
PORT PORT
Layer metal1 ; LAYER metal1 ;
RECT 0.0325 0.0 0.7325 41.725 ; RECT 0.0325 0.0 0.7325 41.725 ;
RECT 12.7675 0.0 13.4675 41.725 ; RECT 12.7675 0.0 13.4675 41.725 ;
END END
@ -19,14 +19,14 @@ MACRO sram_2_16_1_freepdk45
USE GROUND ; USE GROUND ;
SHAPE ABUTMENT ; SHAPE ABUTMENT ;
PORT PORT
Layer metal2 ; LAYER metal2 ;
RECT 8.9225 0.0 9.6225 41.725 ; RECT 8.9225 0.0 9.6225 41.725 ;
END END
END gnd END gnd
PIN DATA[0] PIN DATA[0]
DIRECTION INOUT ; DIRECTION INOUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 11.48 0.0 11.55 3.22 ; RECT 11.48 0.0 11.55 3.22 ;
RECT 11.48 0.0 11.55 0.135 ; RECT 11.48 0.0 11.55 0.135 ;
END END
@ -34,7 +34,7 @@ MACRO sram_2_16_1_freepdk45
PIN DATA[1] PIN DATA[1]
DIRECTION INOUT ; DIRECTION INOUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 12.185 0.0 12.255 3.22 ; RECT 12.185 0.0 12.255 3.22 ;
RECT 12.185 0.0 12.255 0.135 ; RECT 12.185 0.0 12.255 0.135 ;
END END
@ -42,62 +42,62 @@ MACRO sram_2_16_1_freepdk45
PIN ADDR[0] PIN ADDR[0]
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 0.0325 7.4525 1.015 7.5225 ; RECT 0.0325 7.4525 1.015 7.5225 ;
END END
END ADDR[0] END ADDR[0]
PIN ADDR[1] PIN ADDR[1]
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 0.0325 6.7475 1.015 6.8175 ; RECT 0.0325 6.7475 1.015 6.8175 ;
END END
END ADDR[1] END ADDR[1]
PIN ADDR[2] PIN ADDR[2]
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 0.0325 6.0425 1.015 6.1125 ; RECT 0.0325 6.0425 1.015 6.1125 ;
END END
END ADDR[2] END ADDR[2]
PIN ADDR[3] PIN ADDR[3]
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 0.0325 5.3375 1.015 5.4075 ; RECT 0.0325 5.3375 1.015 5.4075 ;
END END
END ADDR[3] END ADDR[3]
PIN CSb PIN CSb
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT -5.4125 8.275 -5.3425 8.415 ; RECT -5.4125 8.275 -5.3425 8.415 ;
END END
END CSb END CSb
PIN OEb PIN OEb
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT -4.0025 8.275 -3.9325 8.415 ; RECT -4.0025 8.275 -3.9325 8.415 ;
END END
END OEb END OEb
PIN WEb PIN WEb
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT -4.7075 8.275 -4.6375 8.415 ; RECT -4.7075 8.275 -4.6375 8.415 ;
END END
END WEb END WEb
PIN clk PIN clk
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT -2.0525 8.275 9.7625 8.345 ; RECT -2.0525 8.275 9.7625 8.345 ;
RECT -2.085 8.275 -2.015 8.41 ; RECT -2.085 8.275 -2.015 8.41 ;
END END
END clk END clk
OBS OBS
Layer metal1 ; LAYER metal1 ;
RECT -0.545 26.2975 0.0325 26.3625 ; RECT -0.545 26.2975 0.0325 26.3625 ;
RECT 12.7675 0.0 13.4675 41.725 ; RECT 12.7675 0.0 13.4675 41.725 ;
RECT 0.0325 0.0 0.7325 41.725 ; RECT 0.0325 0.0 0.7325 41.725 ;
@ -7449,7 +7449,7 @@ MACRO sram_2_16_1_freepdk45
RECT -1.0825 16.8675 -0.9475 16.9325 ; RECT -1.0825 16.8675 -0.9475 16.9325 ;
RECT -1.035 17.3375 -0.9 17.4025 ; RECT -1.035 17.3375 -0.9 17.4025 ;
RECT 0.0325 19.855 0.2375 19.99 ; RECT 0.0325 19.855 0.2375 19.99 ;
Layer via1 ; LAYER via1 ;
RECT 11.835 19.68 11.9 19.745 ; RECT 11.835 19.68 11.9 19.745 ;
RECT 11.835 19.68 11.9 19.745 ; RECT 11.835 19.68 11.9 19.745 ;
RECT 11.835 19.68 11.9 19.745 ; RECT 11.835 19.68 11.9 19.745 ;
@ -9252,7 +9252,7 @@ MACRO sram_2_16_1_freepdk45
RECT -1.0 17.3375 -0.935 17.4025 ; RECT -1.0 17.3375 -0.935 17.4025 ;
RECT 0.0325 19.89 0.0975 19.955 ; RECT 0.0325 19.89 0.0975 19.955 ;
RECT 0.1725 19.89 0.2375 19.955 ; RECT 0.1725 19.89 0.2375 19.955 ;
Layer metal2 ; LAYER metal2 ;
RECT -0.35 19.855 0.0325 19.925 ; RECT -0.35 19.855 0.0325 19.925 ;
RECT 8.9225 0.0 9.6225 41.725 ; RECT 8.9225 0.0 9.6225 41.725 ;
RECT 10.8125 0.0 10.8825 41.725 ; RECT 10.8125 0.0 10.8825 41.725 ;
@ -11796,7 +11796,7 @@ MACRO sram_2_16_1_freepdk45
RECT 0.0325 19.855 0.2375 19.99 ; RECT 0.0325 19.855 0.2375 19.99 ;
RECT 8.9225 20.695 9.1275 20.83 ; RECT 8.9225 20.695 9.1275 20.83 ;
RECT -0.415 20.695 -0.28 20.765 ; RECT -0.415 20.695 -0.28 20.765 ;
Layer via2 ; LAYER via2 ;
RECT 11.475 18.79 11.545 18.86 ; RECT 11.475 18.79 11.545 18.86 ;
RECT 12.18 18.79 12.25 18.86 ; RECT 12.18 18.79 12.25 18.86 ;
RECT 11.48 9.87 11.55 9.94 ; RECT 11.48 9.87 11.55 9.94 ;
@ -11845,7 +11845,7 @@ MACRO sram_2_16_1_freepdk45
RECT 8.9225 20.73 8.9875 20.795 ; RECT 8.9225 20.73 8.9875 20.795 ;
RECT 9.0625 20.73 9.1275 20.795 ; RECT 9.0625 20.73 9.1275 20.795 ;
RECT -0.38 20.6975 -0.315 20.7625 ; RECT -0.38 20.6975 -0.315 20.7625 ;
Layer metal3 ; LAYER metal3 ;
RECT -2.0525 8.275 9.7625 8.345 ; RECT -2.0525 8.275 9.7625 8.345 ;
RECT -0.14 15.975 10.3925 16.045 ; RECT -0.14 15.975 10.3925 16.045 ;
RECT -0.14 8.415 10.1825 8.485 ; RECT -0.14 8.415 10.1825 8.485 ;

34
compiler/tests/golden/sram_2_16_1_scn3me_subm.lef
View File

@ -9,7 +9,7 @@ MACRO sram_2_16_1_scn3me_subm
USE POWER ; USE POWER ;
SHAPE ABUTMENT ; SHAPE ABUTMENT ;
PORT PORT
Layer metal1 ; LAYER metal1 ;
RECT 0.45 0.0 9.45 459.3 ; RECT 0.45 0.0 9.45 459.3 ;
RECT 147.45 0.0 156.45 459.3 ; RECT 147.45 0.0 156.45 459.3 ;
END END
@ -19,14 +19,14 @@ MACRO sram_2_16_1_scn3me_subm
USE GROUND ; USE GROUND ;
SHAPE ABUTMENT ; SHAPE ABUTMENT ;
PORT PORT
Layer metal2 ; LAYER metal2 ;
RECT 95.55 0.0 104.55 459.3 ; RECT 95.55 0.0 104.55 459.3 ;
END END
END gnd END gnd
PIN DATA[0] PIN DATA[0]
DIRECTION INOUT ; DIRECTION INOUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 128.7 0.0 130.2 30.15 ; RECT 128.7 0.0 130.2 30.15 ;
RECT 128.7 0.0 130.5 1.8 ; RECT 128.7 0.0 130.5 1.8 ;
END END
@ -34,7 +34,7 @@ MACRO sram_2_16_1_scn3me_subm
PIN DATA[1] PIN DATA[1]
DIRECTION INOUT ; DIRECTION INOUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 138.9 0.0 140.4 30.15 ; RECT 138.9 0.0 140.4 30.15 ;
RECT 138.9 0.0 140.7 1.8 ; RECT 138.9 0.0 140.7 1.8 ;
END END
@ -42,62 +42,62 @@ MACRO sram_2_16_1_scn3me_subm
PIN ADDR[0] PIN ADDR[0]
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 0.45 73.95 17.55 75.45 ; RECT 0.45 73.95 17.55 75.45 ;
END END
END ADDR[0] END ADDR[0]
PIN ADDR[1] PIN ADDR[1]
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 0.45 63.75 17.55 65.25 ; RECT 0.45 63.75 17.55 65.25 ;
END END
END ADDR[1] END ADDR[1]
PIN ADDR[2] PIN ADDR[2]
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 0.45 53.55 17.55 55.05 ; RECT 0.45 53.55 17.55 55.05 ;
END END
END ADDR[2] END ADDR[2]
PIN ADDR[3] PIN ADDR[3]
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT 0.45 43.35 17.55 44.85 ; RECT 0.45 43.35 17.55 44.85 ;
END END
END ADDR[3] END ADDR[3]
PIN CSb PIN CSb
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT -62.1 86.4 -60.3 88.2 ; RECT -62.1 86.4 -60.3 88.2 ;
END END
END CSb END CSb
PIN OEb PIN OEb
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT -41.7 86.4 -39.9 88.2 ; RECT -41.7 86.4 -39.9 88.2 ;
END END
END OEb END OEb
PIN WEb PIN WEb
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT -51.9 86.4 -50.1 88.2 ; RECT -51.9 86.4 -50.1 88.2 ;
END END
END WEb END WEb
PIN clk PIN clk
DIRECTION INPUT ; DIRECTION INPUT ;
PORT PORT
Layer metal3 ; LAYER metal3 ;
RECT -27.15 85.5 106.35 87.0 ; RECT -27.15 85.5 106.35 87.0 ;
RECT -27.6 85.5 -25.8 87.3 ; RECT -27.6 85.5 -25.8 87.3 ;
END END
END clk END clk
OBS OBS
Layer metal1 ; LAYER metal1 ;
RECT -10.2 293.55 0.45 294.45 ; RECT -10.2 293.55 0.45 294.45 ;
RECT 147.45 0.0 156.45 459.3 ; RECT 147.45 0.0 156.45 459.3 ;
RECT 0.45 0.0 9.45 459.3 ; RECT 0.45 0.0 9.45 459.3 ;
@ -4773,7 +4773,7 @@ MACRO sram_2_16_1_scn3me_subm
RECT -15.0 175.5 -13.8 176.7 ; RECT -15.0 175.5 -13.8 176.7 ;
RECT -15.0 180.0 -13.8 181.2 ; RECT -15.0 180.0 -13.8 181.2 ;
RECT 0.45 219.6 2.85 220.8 ; RECT 0.45 219.6 2.85 220.8 ;
Layer via1 ; LAYER via1 ;
RECT 125.25 209.7 125.85 210.3 ; RECT 125.25 209.7 125.85 210.3 ;
RECT 134.25 209.7 134.85 210.3 ; RECT 134.25 209.7 134.85 210.3 ;
RECT 126.15 200.4 126.75 201.0 ; RECT 126.15 200.4 126.75 201.0 ;
@ -5392,7 +5392,7 @@ MACRO sram_2_16_1_scn3me_subm
RECT -14.7 180.3 -14.1 180.9 ; RECT -14.7 180.3 -14.1 180.9 ;
RECT 0.75 219.9 1.35 220.5 ; RECT 0.75 219.9 1.35 220.5 ;
RECT 1.95 219.9 2.55 220.5 ; RECT 1.95 219.9 2.55 220.5 ;
Layer metal2 ; LAYER metal2 ;
RECT -7.5 219.6 0.45 220.5 ; RECT -7.5 219.6 0.45 220.5 ;
RECT 95.55 0.0 104.55 459.3 ; RECT 95.55 0.0 104.55 459.3 ;
RECT 119.85 0.0 120.75 459.3 ; RECT 119.85 0.0 120.75 459.3 ;
@ -6442,7 +6442,7 @@ MACRO sram_2_16_1_scn3me_subm
RECT 0.45 219.6 2.85 220.8 ; RECT 0.45 219.6 2.85 220.8 ;
RECT 95.85 230.7 98.55 231.9 ; RECT 95.85 230.7 98.55 231.9 ;
RECT -8.1 230.7 -6.9 231.9 ; RECT -8.1 230.7 -6.9 231.9 ;
Layer via2 ; LAYER via2 ;
RECT 125.55 152.7 126.15 153.3 ; RECT 125.55 152.7 126.15 153.3 ;
RECT 135.75 152.7 136.35 153.3 ; RECT 135.75 152.7 136.35 153.3 ;
RECT 129.15 32.4 129.75 33.0 ; RECT 129.15 32.4 129.75 33.0 ;
@ -6489,7 +6489,7 @@ MACRO sram_2_16_1_scn3me_subm
RECT 96.15 231.0 96.75 231.6 ; RECT 96.15 231.0 96.75 231.6 ;
RECT 97.65 231.0 98.25 231.6 ; RECT 97.65 231.0 98.25 231.6 ;
RECT -7.8 231.0 -7.2 231.6 ; RECT -7.8 231.0 -7.2 231.6 ;
Layer metal3 ; LAYER metal3 ;
RECT -27.15 85.5 106.35 87.0 ; RECT -27.15 85.5 106.35 87.0 ;
RECT -3.0 161.7 114.45 163.2 ; RECT -3.0 161.7 114.45 163.2 ;
RECT -3.0 88.5 111.75 90.0 ; RECT -3.0 88.5 111.75 90.0 ;