diff --git a/compiler/lef.py b/compiler/lef.py index e8911e54..7bb3945f 100644 --- a/compiler/lef.py +++ b/compiler/lef.py @@ -45,11 +45,11 @@ class lef: for pin in input_pin_name: self.writePin(pin,4) - self.lef.write(" OBS \n") + self.lef.write(" OBS\n") for lay in self.layer: - self.lef.write(" Layer {0} ; \n".format(lay)) + self.lef.write(" LAYER {0} ;\n".format(lay)) self.writeObstruct(self.sr.name, lay, mirr = 1, angle = math.radians(float(0)), xyShift = (0, 0)) - self.lef.write(" END \n") + self.lef.write(" END\n") self.writeLefFooter() @@ -160,8 +160,8 @@ class lef: self.lef.write(" SYMMETRY X Y R90 ;\n") def writeLefFooter(self): - self.lef.write("END {0} \n".format(self.sr.name)) - self.lef.write("END LIBRARY \n") + self.lef.write("END {0}\n".format(self.sr.name)) + self.lef.write("END LIBRARY\n") def powerPinName(self): return ["vdd"] @@ -187,35 +187,35 @@ class lef: return inout_pin_name def writePin(self, pinName, typ): - self.lef.write(" PIN {0} \n".format(pinName)) + self.lef.write(" PIN {0}\n".format(pinName)) if typ == 1: - self.lef.write(" DIRECTION INOUT ; \n") - self.lef.write(" USE POWER ; \n") - self.lef.write(" SHAPE ABUTMENT ; \n") - self.lef.write(" PORT \n") + self.lef.write(" DIRECTION INOUT ;\n") + self.lef.write(" USE POWER ;\n") + self.lef.write(" SHAPE ABUTMENT ;\n") + self.lef.write(" PORT\n") elif typ == 2: - self.lef.write(" DIRECTION INOUT ; \n") - self.lef.write(" USE GROUND ; \n") - self.lef.write(" SHAPE ABUTMENT ; \n") - self.lef.write(" PORT \n") + self.lef.write(" DIRECTION INOUT ;\n") + self.lef.write(" USE GROUND ;\n") + self.lef.write(" SHAPE ABUTMENT ;\n") + self.lef.write(" PORT\n") elif typ == 3: - self.lef.write(" DIRECTION INOUT ; \n") - self.lef.write(" PORT \n") + self.lef.write(" DIRECTION INOUT ;\n") + self.lef.write(" PORT\n") elif typ == 4: - self.lef.write(" DIRECTION INPUT ; \n") - self.lef.write(" PORT \n") + self.lef.write(" DIRECTION INPUT ;\n") + self.lef.write(" PORT\n") else: debug.error("Invalid pin type on pin {0}".format(pinName)) pin_layer_coord = self.pinLayerCoord(self.sr.name, pinName) for pinLayer in pin_layer_coord: lay = [key for key, value in tech.layer.iteritems() if value == pinLayer][0] - self.lef.write(" Layer {0} ; \n".format(lay)) + self.lef.write(" LAYER {0} ;\n".format(lay)) for pinCoord in pin_layer_coord[pinLayer]: self.writePinCoord(self.sr.name, pinName, pinLayer, pinCoord, mirr = 1,angle = math.radians(float(0)), xyShift = (0, 0)) - self.lef.write(" END \n") - self.lef.write(" END {0} \n".format(pinName)) + self.lef.write(" END\n") + self.lef.write(" END {0}\n".format(pinName)) def lowestLeftCorner(self, sr, mirr = 1, angle = math.radians(float(0)), xyShift = (0, 0), listMinX = [], listMinY = [], listMaxX = [], listMaxY =[]): """Recursive find a lowest left conner on each Structure in GDS file""" diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.lef b/compiler/tests/golden/sram_2_16_1_freepdk45.lef index dc3d1671..00aaa3cd 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.lef +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.lef @@ -4,100 +4,100 @@ MACRO sram_2_16_1_freepdk45 FOREIGN sram 0.0 0.0 ; SIZE 19.165 BY 41.725 ; SYMMETRY X Y R90 ; - PIN vdd - DIRECTION INOUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - Layer metal1 ; + PIN vdd + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; RECT 0.0325 0.0 0.7325 41.725 ; RECT 12.7675 0.0 13.4675 41.725 ; - END - END vdd - PIN gnd - DIRECTION INOUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - Layer metal2 ; + END + END vdd + PIN gnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal2 ; RECT 8.9225 0.0 9.6225 41.725 ; - END - END gnd - PIN DATA[0] - DIRECTION INOUT ; - PORT - Layer metal3 ; + END + END gnd + PIN DATA[0] + DIRECTION INOUT ; + PORT + LAYER metal3 ; RECT 11.48 0.0 11.55 3.22 ; RECT 11.48 0.0 11.55 0.135 ; - END - END DATA[0] - PIN DATA[1] - DIRECTION INOUT ; - PORT - Layer metal3 ; + END + END DATA[0] + PIN DATA[1] + DIRECTION INOUT ; + PORT + LAYER metal3 ; RECT 12.185 0.0 12.255 3.22 ; RECT 12.185 0.0 12.255 0.135 ; - END - END DATA[1] - PIN ADDR[0] - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END DATA[1] + PIN ADDR[0] + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT 0.0325 7.4525 1.015 7.5225 ; - END - END ADDR[0] - PIN ADDR[1] - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END ADDR[0] + PIN ADDR[1] + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT 0.0325 6.7475 1.015 6.8175 ; - END - END ADDR[1] - PIN ADDR[2] - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END ADDR[1] + PIN ADDR[2] + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT 0.0325 6.0425 1.015 6.1125 ; - END - END ADDR[2] - PIN ADDR[3] - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END ADDR[2] + PIN ADDR[3] + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT 0.0325 5.3375 1.015 5.4075 ; - END - END ADDR[3] - PIN CSb - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END ADDR[3] + PIN CSb + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT -5.4125 8.275 -5.3425 8.415 ; - END - END CSb - PIN OEb - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END CSb + PIN OEb + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT -4.0025 8.275 -3.9325 8.415 ; - END - END OEb - PIN WEb - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END OEb + PIN WEb + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT -4.7075 8.275 -4.6375 8.415 ; - END - END WEb - PIN clk - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END WEb + PIN clk + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT -2.0525 8.275 9.7625 8.345 ; RECT -2.085 8.275 -2.015 8.41 ; - END - END clk - OBS - Layer metal1 ; + END + END clk + OBS + LAYER metal1 ; RECT -0.545 26.2975 0.0325 26.3625 ; RECT 12.7675 0.0 13.4675 41.725 ; RECT 0.0325 0.0 0.7325 41.725 ; @@ -7449,7 +7449,7 @@ MACRO sram_2_16_1_freepdk45 RECT -1.0825 16.8675 -0.9475 16.9325 ; RECT -1.035 17.3375 -0.9 17.4025 ; RECT 0.0325 19.855 0.2375 19.99 ; - Layer via1 ; + LAYER via1 ; RECT 11.835 19.68 11.9 19.745 ; RECT 11.835 19.68 11.9 19.745 ; RECT 11.835 19.68 11.9 19.745 ; @@ -9252,7 +9252,7 @@ MACRO sram_2_16_1_freepdk45 RECT -1.0 17.3375 -0.935 17.4025 ; RECT 0.0325 19.89 0.0975 19.955 ; RECT 0.1725 19.89 0.2375 19.955 ; - Layer metal2 ; + LAYER metal2 ; RECT -0.35 19.855 0.0325 19.925 ; RECT 8.9225 0.0 9.6225 41.725 ; RECT 10.8125 0.0 10.8825 41.725 ; @@ -11796,7 +11796,7 @@ MACRO sram_2_16_1_freepdk45 RECT 0.0325 19.855 0.2375 19.99 ; RECT 8.9225 20.695 9.1275 20.83 ; RECT -0.415 20.695 -0.28 20.765 ; - Layer via2 ; + LAYER via2 ; RECT 11.475 18.79 11.545 18.86 ; RECT 12.18 18.79 12.25 18.86 ; RECT 11.48 9.87 11.55 9.94 ; @@ -11845,7 +11845,7 @@ MACRO sram_2_16_1_freepdk45 RECT 8.9225 20.73 8.9875 20.795 ; RECT 9.0625 20.73 9.1275 20.795 ; RECT -0.38 20.6975 -0.315 20.7625 ; - Layer metal3 ; + LAYER metal3 ; RECT -2.0525 8.275 9.7625 8.345 ; RECT -0.14 15.975 10.3925 16.045 ; RECT -0.14 8.415 10.1825 8.485 ; @@ -11921,6 +11921,6 @@ MACRO sram_2_16_1_freepdk45 RECT 10.7475 17.335 10.8825 17.405 ; RECT 8.9225 20.695 9.1275 20.83 ; RECT -0.415 20.695 -0.28 20.765 ; - END -END sram_2_16_1_freepdk45 -END LIBRARY + END +END sram_2_16_1_freepdk45 +END LIBRARY diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef index 812abb23..d2f408e7 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lef @@ -4,100 +4,100 @@ MACRO sram_2_16_1_scn3me_subm FOREIGN sram 0.0 0.0 ; SIZE 222.3 BY 459.3 ; SYMMETRY X Y R90 ; - PIN vdd - DIRECTION INOUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - Layer metal1 ; + PIN vdd + DIRECTION INOUT ; + USE POWER ; + SHAPE ABUTMENT ; + PORT + LAYER metal1 ; RECT 0.45 0.0 9.45 459.3 ; RECT 147.45 0.0 156.45 459.3 ; - END - END vdd - PIN gnd - DIRECTION INOUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - Layer metal2 ; + END + END vdd + PIN gnd + DIRECTION INOUT ; + USE GROUND ; + SHAPE ABUTMENT ; + PORT + LAYER metal2 ; RECT 95.55 0.0 104.55 459.3 ; - END - END gnd - PIN DATA[0] - DIRECTION INOUT ; - PORT - Layer metal3 ; + END + END gnd + PIN DATA[0] + DIRECTION INOUT ; + PORT + LAYER metal3 ; RECT 128.7 0.0 130.2 30.15 ; RECT 128.7 0.0 130.5 1.8 ; - END - END DATA[0] - PIN DATA[1] - DIRECTION INOUT ; - PORT - Layer metal3 ; + END + END DATA[0] + PIN DATA[1] + DIRECTION INOUT ; + PORT + LAYER metal3 ; RECT 138.9 0.0 140.4 30.15 ; RECT 138.9 0.0 140.7 1.8 ; - END - END DATA[1] - PIN ADDR[0] - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END DATA[1] + PIN ADDR[0] + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT 0.45 73.95 17.55 75.45 ; - END - END ADDR[0] - PIN ADDR[1] - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END ADDR[0] + PIN ADDR[1] + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT 0.45 63.75 17.55 65.25 ; - END - END ADDR[1] - PIN ADDR[2] - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END ADDR[1] + PIN ADDR[2] + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT 0.45 53.55 17.55 55.05 ; - END - END ADDR[2] - PIN ADDR[3] - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END ADDR[2] + PIN ADDR[3] + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT 0.45 43.35 17.55 44.85 ; - END - END ADDR[3] - PIN CSb - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END ADDR[3] + PIN CSb + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT -62.1 86.4 -60.3 88.2 ; - END - END CSb - PIN OEb - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END CSb + PIN OEb + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT -41.7 86.4 -39.9 88.2 ; - END - END OEb - PIN WEb - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END OEb + PIN WEb + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT -51.9 86.4 -50.1 88.2 ; - END - END WEb - PIN clk - DIRECTION INPUT ; - PORT - Layer metal3 ; + END + END WEb + PIN clk + DIRECTION INPUT ; + PORT + LAYER metal3 ; RECT -27.15 85.5 106.35 87.0 ; RECT -27.6 85.5 -25.8 87.3 ; - END - END clk - OBS - Layer metal1 ; + END + END clk + OBS + LAYER metal1 ; RECT -10.2 293.55 0.45 294.45 ; RECT 147.45 0.0 156.45 459.3 ; RECT 0.45 0.0 9.45 459.3 ; @@ -4773,7 +4773,7 @@ MACRO sram_2_16_1_scn3me_subm RECT -15.0 175.5 -13.8 176.7 ; RECT -15.0 180.0 -13.8 181.2 ; RECT 0.45 219.6 2.85 220.8 ; - Layer via1 ; + LAYER via1 ; RECT 125.25 209.7 125.85 210.3 ; RECT 134.25 209.7 134.85 210.3 ; RECT 126.15 200.4 126.75 201.0 ; @@ -5392,7 +5392,7 @@ MACRO sram_2_16_1_scn3me_subm RECT -14.7 180.3 -14.1 180.9 ; RECT 0.75 219.9 1.35 220.5 ; RECT 1.95 219.9 2.55 220.5 ; - Layer metal2 ; + LAYER metal2 ; RECT -7.5 219.6 0.45 220.5 ; RECT 95.55 0.0 104.55 459.3 ; RECT 119.85 0.0 120.75 459.3 ; @@ -6442,7 +6442,7 @@ MACRO sram_2_16_1_scn3me_subm RECT 0.45 219.6 2.85 220.8 ; RECT 95.85 230.7 98.55 231.9 ; RECT -8.1 230.7 -6.9 231.9 ; - Layer via2 ; + LAYER via2 ; RECT 125.55 152.7 126.15 153.3 ; RECT 135.75 152.7 136.35 153.3 ; RECT 129.15 32.4 129.75 33.0 ; @@ -6489,7 +6489,7 @@ MACRO sram_2_16_1_scn3me_subm RECT 96.15 231.0 96.75 231.6 ; RECT 97.65 231.0 98.25 231.6 ; RECT -7.8 231.0 -7.2 231.6 ; - Layer metal3 ; + LAYER metal3 ; RECT -27.15 85.5 106.35 87.0 ; RECT -3.0 161.7 114.45 163.2 ; RECT -3.0 88.5 111.75 90.0 ; @@ -6563,6 +6563,6 @@ MACRO sram_2_16_1_scn3me_subm RECT 118.95 180.0 120.75 181.8 ; RECT 95.55 230.4 98.85 232.2 ; RECT -8.4 230.4 -6.6 232.2 ; - END -END sram_2_16_1_scn3me_subm -END LIBRARY + END +END sram_2_16_1_scn3me_subm +END LIBRARY