mirror of https://github.com/VLSIDA/OpenRAM.git
radically simplify unused wordline routing code... bit of a facepalm tbh
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@ -384,12 +384,10 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
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self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
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# Ground the unused replica wordlines
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# Ground the unused replica wordlines
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for (names, inst) in zip(self.replica_bitcell_array.rbl_wordline_names, self.replica_bitcell_array.dummy_row_replica_insts):
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for wl_name in self.unused_wordline_names:
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for (wl_name, pin_name) in zip(names, self.replica_bitcell_array.dummy_row.get_wordline_names()):
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pin = self.replica_bitcell_array_inst.get_pin(wl_name)
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if wl_name in self.unused_wordline_names:
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self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
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pin = inst.get_pin(pin_name)
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self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
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self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x, self.array_offset)
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self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x, self.array_offset)
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def route_side_pin(self, name, side, offset_multiple=1):
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def route_side_pin(self, name, side, offset_multiple=1):
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"""
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"""
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@ -459,23 +457,23 @@ class capped_replica_bitcell_array(bitcell_base_array):
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return (left_loc, right_loc)
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return (left_loc, right_loc)
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def connect_side_pin(self, pin, side, offset, inst_offset=vector(0, 0)):
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def connect_side_pin(self, pin, side, offset):
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"""
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"""
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Used to connect horizontal layers of pins to the left/right straps
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Used to connect horizontal layers of pins to the left/right straps
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locs provides the offsets of the pin strip end points.
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locs provides the offsets of the pin strip end points.
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"""
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"""
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if side in ["left", "right"]:
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if side in ["left", "right"]:
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self.connect_vertical_side_pin(pin, side, offset, inst_offset)
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self.connect_vertical_side_pin(pin, side, offset)
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elif side in ["top", "bottom", "bot"]:
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elif side in ["top", "bottom", "bot"]:
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self.connect_horizontal_side_pin(pin, side, offset, inst_offset)
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self.connect_horizontal_side_pin(pin, side, offset)
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else:
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else:
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debug.error("Invalid side {}".format(side), -1)
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debug.error("Invalid side {}".format(side), -1)
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def connect_horizontal_side_pin(self, pin, side, yoffset, inst_offset=vector(0, 0)):
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def connect_horizontal_side_pin(self, pin, side, yoffset):
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"""
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"""
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Used to connect vertical layers of pins to the top/bottom horizontal straps
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Used to connect vertical layers of pins to the top/bottom horizontal straps
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"""
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"""
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cell_loc = pin.center() + inst_offset
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cell_loc = pin.center()
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pin_loc = vector(cell_loc.x, yoffset)
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pin_loc = vector(cell_loc.x, yoffset)
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# Place the pins a track outside of the array
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# Place the pins a track outside of the array
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@ -488,11 +486,11 @@ class capped_replica_bitcell_array(bitcell_base_array):
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self.add_path(pin.layer, [cell_loc, pin_loc])
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self.add_path(pin.layer, [cell_loc, pin_loc])
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def connect_vertical_side_pin(self, pin, side, xoffset, inst_offset=vector(0, 0)):
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def connect_vertical_side_pin(self, pin, side, xoffset):
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"""
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"""
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Used to connect vertical layers of pins to the top/bottom vertical straps
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Used to connect vertical layers of pins to the top/bottom vertical straps
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"""
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"""
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cell_loc = pin.center() + inst_offset
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cell_loc = pin.center()
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pin_loc = vector(xoffset, cell_loc.y)
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pin_loc = vector(xoffset, cell_loc.y)
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# Place the pins a track outside of the array
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# Place the pins a track outside of the array
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