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Convert unit tests to use new options as well.

This commit is contained in:
Matt Guthaus 2018-01-19 17:23:38 -08:00
parent 95fab1ca71
commit 84ec7a5be0
9 changed files with 22 additions and 22 deletions
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6
compiler/tests/21_hspice_delay_test.py
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@ -26,9 +26,9 @@ class timing_sram_test(unittest.TestCase):
import sram import sram
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size, s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="sram1") name="sram1")
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True

6
compiler/tests/21_ngspice_delay_test.py
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@ -26,9 +26,9 @@ class timing_sram_test(unittest.TestCase):
import sram import sram
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size, s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="sram1") name="sram1")
tempspice = OPTS.openram_temp + "temp.sp" tempspice = OPTS.openram_temp + "temp.sp"

6
compiler/tests/22_pex_func_test_with_pinv.py
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@ -33,9 +33,9 @@ class sram_func_test(unittest.TestCase):
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
OPTS.check_lvsdrc = False OPTS.check_lvsdrc = False
OPTS.use_pex = True OPTS.use_pex = True
s = sram.sram(word_size=OPTS.config.word_size, s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="test_sram1") name="test_sram1")
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True
OPTS.use_pex = False OPTS.use_pex = False

6
compiler/tests/22_sram_func_test.py
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@ -25,9 +25,9 @@ class sram_func_test(unittest.TestCase):
import sram import sram
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size, s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="sram_func_test") name="sram_func_test")
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True

4
compiler/tests/23_lib_sram_model_test.py
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@ -22,8 +22,8 @@ class lib_test(unittest.TestCase):
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank") debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2, s = sram.sram(word_size=2,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name)) name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True

4
compiler/tests/23_lib_sram_prune_test.py
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@ -26,8 +26,8 @@ class lib_test(unittest.TestCase):
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank") debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2, s = sram.sram(word_size=2,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name)) name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True

4
compiler/tests/23_lib_sram_test.py
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@ -26,8 +26,8 @@ class lib_test(unittest.TestCase):
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank") debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2, s = sram.sram(word_size=2,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name)) name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True

4
compiler/tests/24_lef_sram_test.py
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@ -22,8 +22,8 @@ class lef_test(unittest.TestCase):
debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank") debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2, s = sram.sram(word_size=2,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name)) name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True

4
compiler/tests/25_verilog_sram_test.py
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@ -22,8 +22,8 @@ class verilog_test(unittest.TestCase):
debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank") debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2, s = sram.sram(word_size=2,
num_words=OPTS.config.num_words, num_words=OPTS.num_words,
num_banks=OPTS.config.num_banks, num_banks=OPTS.num_banks,
name="sram_2_16_1_{0}".format(OPTS.tech_name)) name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True OPTS.check_lvsdrc = True