From 84ec7a5be0542e0f0cfeb0d52707107020cb82e1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 19 Jan 2018 17:23:38 -0800 Subject: [PATCH] Convert unit tests to use new options as well. --- compiler/tests/21_hspice_delay_test.py | 6 +++--- compiler/tests/21_ngspice_delay_test.py | 6 +++--- compiler/tests/22_pex_func_test_with_pinv.py | 6 +++--- compiler/tests/22_sram_func_test.py | 6 +++--- compiler/tests/23_lib_sram_model_test.py | 4 ++-- compiler/tests/23_lib_sram_prune_test.py | 4 ++-- compiler/tests/23_lib_sram_test.py | 4 ++-- compiler/tests/24_lef_sram_test.py | 4 ++-- compiler/tests/25_verilog_sram_test.py | 4 ++-- 9 files changed, 22 insertions(+), 22 deletions(-) diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 157f6a12..20372191 100644 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -26,9 +26,9 @@ class timing_sram_test(unittest.TestCase): import sram debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") - s = sram.sram(word_size=OPTS.config.word_size, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + s = sram.sram(word_size=OPTS.word_size, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="sram1") OPTS.check_lvsdrc = True diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 98ab4073..82a027e3 100644 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -26,9 +26,9 @@ class timing_sram_test(unittest.TestCase): import sram debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") - s = sram.sram(word_size=OPTS.config.word_size, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + s = sram.sram(word_size=OPTS.word_size, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="sram1") tempspice = OPTS.openram_temp + "temp.sp" diff --git a/compiler/tests/22_pex_func_test_with_pinv.py b/compiler/tests/22_pex_func_test_with_pinv.py index b15bf3df..706d19d6 100644 --- a/compiler/tests/22_pex_func_test_with_pinv.py +++ b/compiler/tests/22_pex_func_test_with_pinv.py @@ -33,9 +33,9 @@ class sram_func_test(unittest.TestCase): debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") OPTS.check_lvsdrc = False OPTS.use_pex = True - s = sram.sram(word_size=OPTS.config.word_size, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + s = sram.sram(word_size=OPTS.word_size, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="test_sram1") OPTS.check_lvsdrc = True OPTS.use_pex = False diff --git a/compiler/tests/22_sram_func_test.py b/compiler/tests/22_sram_func_test.py index da7d09c1..62635a4f 100644 --- a/compiler/tests/22_sram_func_test.py +++ b/compiler/tests/22_sram_func_test.py @@ -25,9 +25,9 @@ class sram_func_test(unittest.TestCase): import sram debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") - s = sram.sram(word_size=OPTS.config.word_size, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + s = sram.sram(word_size=OPTS.word_size, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="sram_func_test") OPTS.check_lvsdrc = True diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index cbdbe8fc..f1d1e8c8 100644 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -22,8 +22,8 @@ class lib_test(unittest.TestCase): debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank") s = sram.sram(word_size=2, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="sram_2_16_1_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = True diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index ea22252f..7a1b32ee 100644 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -26,8 +26,8 @@ class lib_test(unittest.TestCase): debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank") s = sram.sram(word_size=2, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="sram_2_16_1_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index b1aae5d1..7244760e 100644 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -26,8 +26,8 @@ class lib_test(unittest.TestCase): debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank") s = sram.sram(word_size=2, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="sram_2_16_1_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = True diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index b5400877..e142c1f0 100644 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -22,8 +22,8 @@ class lef_test(unittest.TestCase): debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank") s = sram.sram(word_size=2, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="sram_2_16_1_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = True diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index e6844984..9d74d612 100644 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -22,8 +22,8 @@ class verilog_test(unittest.TestCase): debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank") s = sram.sram(word_size=2, - num_words=OPTS.config.num_words, - num_banks=OPTS.config.num_banks, + num_words=OPTS.num_words, + num_banks=OPTS.num_banks, name="sram_2_16_1_{0}".format(OPTS.tech_name)) OPTS.check_lvsdrc = True