mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-07 11:21:14 +02:00
Move last few modules to base dir
This commit is contained in:
Matt Guthaus
@@ -0,0 +1,115 @@
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import gdsMill
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import tech
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import globals
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import math
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import debug
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import datetime
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from collections import defaultdict
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class lef:
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"""
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SRAM LEF Class open GDS file, read pins information, obstruction
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and write them to LEF file
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"""
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def __init__(self,layers):
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# LEF db units per micron
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self.lef_units = 1000
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# These are the layers of the obstructions
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self.lef_layers = layers
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def lef_write(self, lef_name):
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"""Write the entire lef of the object to the file."""
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debug.info(3, "Writing to {0}".format(lef_name))
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self.indent = "" # To maintain the indent level easily
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self.lef = open(lef_name,"w")
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self.lef_write_header()
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for pin in self.pins:
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self.lef_write_pin(pin)
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self.lef_write_obstructions()
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self.lef_write_footer()
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self.lef.close()
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def lef_write_header(self):
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""" Header of LEF file """
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self.lef.write("VERSION 5.4 ;\n")
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self.lef.write("NAMESCASESENSITIVE ON ;\n")
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self.lef.write("BUSBITCHARS \"[]\" ;\n")
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self.lef.write("DIVIDERCHAR \"/\" ;\n")
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self.lef.write("UNITS\n")
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self.lef.write(" DATABASE MICRONS {0} ;\n".format(self.lef_units))
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self.lef.write("END UNITS\n")
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self.lef.write("SITE MacroSite\n")
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self.indent += " "
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self.lef.write("{0}CLASS Core ;\n".format(self.indent))
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self.lef.write("{0}SIZE {1} by {2} ;\n".format(self.indent,
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self.lef_units*self.width,
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self.lef_units*self.height))
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self.indent = self.indent[:-3]
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self.lef.write("END MacroSite\n")
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self.lef.write("{0}MACRO {1}\n".format(self.indent,self.name))
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self.indent += " "
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self.lef.write("{0}CLASS BLOCK ;\n".format(self.indent))
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self.lef.write("{0}SIZE {1} BY {2} ;\n" .format(self.indent,
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self.lef_units*self.width,
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self.lef_units*self.height))
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self.lef.write("{0}SYMMETRY X Y R90 ;\n".format(self.indent))
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self.lef.write("{0}SITE MacroSite ;\n".format(self.indent))
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def lef_write_footer(self):
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self.lef.write("{0}END {1}\n".format(self.indent,self.name))
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self.indent = self.indent[:-3]
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self.lef.write("END LIBRARY\n")
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def lef_write_pin(self, name):
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pin_dir = self.get_pin_dir(name)
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pin_type = self.get_pin_type(name)
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self.lef.write("{0}PIN {1}\n".format(self.indent,name))
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self.indent += " "
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self.lef.write("{0}DIRECTION {1} ;\n".format(self.indent,pin_dir))
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if pin_type in ["POWER","GROUND"]:
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self.lef.write("{0}USE {1} ; \n".format(self.indent,pin_type))
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self.lef.write("{0}SHAPE ABUTMENT ; \n".format(self.indent))
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self.lef.write("{0}PORT\n".format(self.indent))
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self.indent += " "
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# We could sort these together to minimize different layer sections, but meh.
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pin_list = self.get_pins(name)
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for pin in pin_list:
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self.lef.write("{0}LAYER {1} ;\n".format(self.indent,pin.layer))
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self.lef_write_rect(pin.rect)
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# End the PORT
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self.indent = self.indent[:-3]
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self.lef.write("{0}END\n".format(self.indent))
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# End the PIN
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self.indent = self.indent[:-3]
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self.lef.write("{0}END {1}\n".format(self.indent,name))
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def lef_write_obstructions(self):
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""" Write all the obstructions on each layer """
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self.lef.write("{0}OBS\n".format(self.indent))
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for layer in self.lef_layers:
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self.lef.write("{0}LAYER {1} ;\n".format(self.indent,layer))
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self.indent += " "
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blockages = self.get_blockages(layer,True)
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for b in blockages:
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self.lef_write_rect(b)
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self.indent = self.indent[:-3]
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self.lef.write("{0}END\n".format(self.indent))
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def lef_write_rect(self, rect):
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""" Write a LEF rectangle """
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self.lef.write("{0}RECT ".format(self.indent))
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for item in rect:
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self.lef.write(" {0} {1}".format(self.lef_units*item[0], self.lef_units*item[1]))
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self.lef.write(" ;\n")
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@@ -0,0 +1,120 @@
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from tech import drc
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import debug
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from contact import contact
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from itertools import tee
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from vector import vector
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from vector3d import vector3d
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class route():
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"""
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Object route (used by the router module)
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Add a route of minimium metal width between a set of points.
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The wire must be completely rectilinear and the
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z-dimension of the points refers to the layers (plus via)
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The points are the center of the wire.
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This can have non-preferred direction routing.
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"""
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def __init__(self, obj, layer_stack, path):
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name = "route_{0}".format(route.unique_route_id)
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route.unique_route_id += 1
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design.design.__init__(self, name)
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debug.info(3, "create route obj {0}".format(name))
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self.obj = obj
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self.layer_stack = layer_stack
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self.path = path
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self.setup_layers()
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self.create_wires()
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def setup_layers(self):
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(horiz_layer, via_layer, vert_layer) = self.layer_stack
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self.via_layer_name = via_layer
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self.vert_layer_name = vert_layer
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self.vert_layer_width = drc["minwidth_{0}".format(vert_layer)]
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self.horiz_layer_name = horiz_layer
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self.horiz_layer_width = drc["minwidth_{0}".format(horiz_layer)]
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# offset this by 1/2 the via size
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self.c=contact(self.layer_stack, (1, 1))
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def create_wires(self):
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"""
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Add the wire segments of the route.
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"""
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def pairwise(iterable):
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"s -> (s0,s1), (s1,s2), (s2, s3), ..."
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a, b = tee(iterable)
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next(b, None)
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return zip(a, b)
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plist = pairwise(self.path)
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for p0,p1 in plist:
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if p0.z != p1.z: # via
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# offset if not rotated
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#via_offset = vector(p0.x+0.5*self.c.width,p0.y+0.5*self.c.height)
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# offset if rotated
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via_offset = vector(p0.x+0.5*self.c.height,p0.y-0.5*self.c.width)
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self.obj.add_via(self.layer_stack,via_offset,rotate=90)
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elif p0.x != p1.x and p0.y != p1.y: # diagonal!
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debug.error("Non-changing direction!")
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else:
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# this will draw an extra corner at the end but that is ok
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self.draw_corner_wire(p1)
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# draw the point to point wire
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self.draw_wire(p0,p1)
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def draw_wire(self, p0, p1):
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"""
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This draws a straight wire with layer_minwidth
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"""
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layer_name = self.layer_stack[2*p0.z]
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layer_width = drc["minwidth_{0}".format(layer_name)]
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# always route left to right or bottom to top
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if p0.z != p1.z:
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self.error("Adding a via as a wire!")
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elif p0.x < p1.x or p0.y < p1.y:
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start = p0
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end = p1
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elif p0.x > p1.x or p0.y > p1.y:
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start = p1
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end = p0
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else:
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debug.error("Neither horizontal or vertical wire.")
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# now determine the route geometry and offset
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if start.x != end.x: # horizontal
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offset = start + vector3d(0,-0.5*layer_width,0)
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height = layer_width
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width = end.x - start.x
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elif start.y != end.y: # vertical
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offset = start + vector3d(-0.5*layer_width,0,0)
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height = end.y - start.y
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width = layer_width
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deisgn.add_rect(layer=layer_name,
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offset=offset,
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width=width,
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height=height)
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def draw_corner_wire(self, p0):
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""" This function adds the corner squares since the center
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line convention only draws to the center of the corner."""
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layer_name = self.layer_stack[2*p0.z]
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layer_width = drc["minwidth_{0}".format(layer_name)]
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offset = vector(p0.x-0.5*layer_width,p0.y-0.5*layer_width)
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self.obj.add_rect(layer=layer_name,
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offset=offset,
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width=layer_width,
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height=layer_width)
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@@ -0,0 +1,60 @@
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import debug
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class verilog:
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""" Create a behavioral Verilog file for simulation."""
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def verilog_write(self,verilog_name):
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""" Write a behavioral Verilog model. """
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self.vf = open(verilog_name, "w")
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self.vf.write("// OpenRAM SRAM model\n")
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self.vf.write("// Words: {0}\n".format(self.num_words))
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self.vf.write("// Word size: {0}\n\n".format(self.word_size))
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self.vf.write("module {0}(DATA,ADDR,CSb,WEb,OEb,clk);\n".format(self.name))
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self.vf.write("\n")
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self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size))
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self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size))
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self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n")
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self.vf.write(" parameter DELAY = 3 ;\n")
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self.vf.write("\n")
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self.vf.write(" inout [DATA_WIDTH-1:0] DATA;\n")
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self.vf.write(" input [ADDR_WIDTH-1:0] ADDR;\n")
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self.vf.write(" input CSb; // active low chip select\n")
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self.vf.write(" input WEb; // active low write control\n")
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self.vf.write(" input OEb; // active output enable\n")
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self.vf.write(" input clk; // clock\n")
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self.vf.write("\n")
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self.vf.write(" reg [DATA_WIDTH-1:0] data_out ;\n")
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self.vf.write(" reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];\n")
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self.vf.write("\n")
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self.vf.write(" // Tri-State Buffer control\n")
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self.vf.write(" // output : When WEb = 1, oeb = 0, csb = 0\n")
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self.vf.write(" assign DATA = (!CSb && !OEb && WEb) ? data_out : {0}'bz;\n".format(self.word_size))
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self.vf.write("\n")
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self.vf.write(" // Memory Write Block\n")
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self.vf.write(" // Write Operation : When WEb = 0, CSb = 0\n")
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self.vf.write(" always @ (posedge clk)\n")
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self.vf.write(" begin : MEM_WRITE\n")
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self.vf.write(" if ( !CSb && !WEb ) begin\n")
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self.vf.write(" mem[ADDR] = DATA;\n")
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self.vf.write(" $display($time,\" Writing %m ABUS=%b DATA=%b\",ADDR,DATA);\n")
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self.vf.write(" end\n")
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self.vf.write(" end\n\n")
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self.vf.write("\n")
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self.vf.write(" // Memory Read Block\n")
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self.vf.write(" // Read Operation : When WEb = 1, CSb = 0\n")
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self.vf.write(" always @ (posedge clk)\n")
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self.vf.write(" begin : MEM_READ\n")
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self.vf.write(" if (!CSb && WEb) begin\n")
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self.vf.write(" data_out <= #(DELAY) mem[ADDR];\n")
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self.vf.write(" $display($time,\" Reading %m ABUS=%b DATA=%b\",ADDR,mem[ADDR]);\n")
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self.vf.write(" end\n")
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self.vf.write(" end\n")
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self.vf.write("\n")
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self.vf.write("endmodule\n")
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self.vf.close()
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